SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS

• US 20070214336A1
• Filed: 03/12/2007
• Published: 09/13/2007
• Est. Priority Date: 03/13/2006
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Shimura, Hidekichi
• Granted Patent: US 7,757,062 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/225 Clock input buffers

Abstract

A semiconductor integrated circuit apparatus that enables function blocks in a semiconductor integrated circuit freely to vary power supply voltage and system clock frequency on the time axis, and also to exchange data among themselves. In a semiconductor integrated circuit apparatus 100, a first function block 110 has a first clock generation circuit 111 that generates a first system clock supplied to circuitry in a function block, first internal memory 112 in which data is read/written by means of the first system clock, and a selector 113 that selects the first system clock or a second system clock and supplies the selected clock to first internal memory 112. A clock selected by selector 113 from the first system clock or the second system clock is supplied as the clock supplied to first internal memory 112.

Claims

1. A semiconductor integrated circuit apparatus comprising:

a first function block that has a first clock generation circuit that generates a first system clock that is supplied to circuitry in a function block, and first internal memory in which data is read/written by means of said first system clock; and

a second function block that has a second clock generation circuit that generates a second system clock that is supplied to circuitry in a function block, and second internal memory in which data is read/written by means of said second system clock;

wherein said first function block has a first selection section that selects said first system clock or said second system clock, and supplies that selected clock to said first internal memory.

2. The semiconductor integrated circuit apparatus according to claim 1, wherein said second function block has a second selection section that selects said first system clock or said second system clock, and supplies that selected clock to said second internal memory.

3. The semiconductor integrated circuit apparatus according to claim 1, wherein:

a frequency of said first system clock is determined depending on an amount of computational processing of said first function block; and

a frequency of said second system clock is determined depending on an amount of computational processing of said second function block.

4. The semiconductor integrated circuit apparatus according to claim 3, wherein a frequency of said first system clock and a frequency of said second system clock have no correlation.

5. The semiconductor integrated circuit apparatus according to claim 1, wherein:

said first clock generation circuit generates said first system clock necessary for performing an amount of computational processing that varies depending on a time axis of said first function block; and

said second clock generation circuit generates said second system clock necessary for performing an amount of computational processing that varies depending on a time axis of said second function block.

6. The semiconductor integrated circuit apparatus according to claim 2, wherein said second selection section, when a data signal in said first function block is written to said second internal memory in said second function block, or when a data signal is read from said second internal memory in said second function block into said first internal memory in said first function block, selects either said first system clock or said second system clock as a clock that is supplied to said second internal memory, and supplies that selected said first system clock to said second internal memory.

7. The semiconductor integrated circuit apparatus according to claim 1, wherein:

said first function block is a general-purpose CPU; and

said second function block is a multifunction DSP.

8. The semiconductor integrated circuit apparatus according to claim 1, wherein:

said second function block is composed of a plurality of function blocks; and

said plurality of function blocks have;

a clock generation circuit that generates a system clock that is supplied to circuitry in that function block; and

internal memory in which data is read/written by means of generated said system clock.

9. The semiconductor integrated circuit apparatus according to claim 1, wherein said internal memory is a register file or cache memory.

10. The semiconductor integrated circuit apparatus according to claim 1, wherein a plurality of function blocks corresponding to said second function block are incorporated.

11. The semiconductor integrated circuit apparatus according to claim 1, wherein a DMA controller controls mutual reading/writing between memories in function blocks corresponding to said plurality of second function blocks.