Semiconductor device and manufacturing method of the same

• US 20070215938A1
• Filed: 03/15/2007
• Published: 09/20/2007
• Est. Priority Date: 03/16/2006
• Status: Abandoned Application

• Current Assignee: Sanyo Semiconductor Company Limited (ON Semiconductor Corporation), Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Semiconductor Company Limited (ON Semiconductor Corporation), Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Kameyama, Koujiro, Okada, Kikuo, Yanagida, Masamichi
• Application Number:
  US11/724,330
• Publication Number:
  US 20070215938A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/41716 Cathode or anode electrodes for thyristors
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7398 with both emitter and collector contacts in the same substrate side
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/10158 at the passive surface

Abstract

Thinning a semiconductor substrate has been needed for reducing on-resistance in a semiconductor device such as a vertical MOS transistor, IGBT, or the like where a high current flows in the semiconductor substrate in a vertical direction. In this case, the thinning is performed to the extent that the semiconductor substrate does not warp with a heat treatment, so that there is a limitation in reduction of on-resistance. In the invention, openings such as trench holes are formed on a back surface side of a semiconductor substrate. Then, a drain electrode is formed being electrically connected with bottoms of these openings. In this case, a current path is formed short corresponding to the depths of the openings, thereby easily achieving low on-resistance.

Claims

1. A semiconductor device comprising:

a semiconductor substrate comprising a front surface and a back surface, a recess portion being formed from the back surface toward the front surface;

a MOS structure formed on the front surface of the semiconductor substrate; and

a back surface electrode formed in the recess portion,

wherein the semiconductor device is configured to form a current flow between the front and back surfaces of the semiconductor substrate.

2. The semiconductor device of claim 1, wherein the semiconductor substrate is of a first general conductive type, the MOS structure comprises a channel layer of a second general conductivity type formed on the front surface of the semiconductor substrate, a plurality of gate insulation films and gate electrodes, a source layer of the first general conductivity type formed adjacent the gate insulation films, a source electrode electrically connected with the source layer and a drain layer electrically connected with the back surface electrode at a bottom of the recess portion, and the back surface electrode comprises a drain electrode.

3. The semiconductor device of claim 1, wherein the semiconductor substrate is of a first general conductive type, the MOS structure comprises a base region of a second general conductive type formed on the front surface of the semiconductor substrate, a plurality of gate insulation films and gate electrodes, a emitter region of the first general conductivity type formed adjacent the gate insulation films, an emitter electrode electrically connected with the emitter region and a collector region of the second general conductivity type electrically connected with the back surface electrode at a bottom of the recess portion, and the back surface electrode comprises a collector electrode.

4. The semiconductor device of claim 1, wherein the semiconductor substrate has a thickness sufficient for mechanically supporting the semiconductor device.

5. The semiconductor device of claim 2, wherein the gate electrode is of a trench type.

6. The semiconductor device of claim 2, wherein the recess portion is formed under the source layer.

7. The semiconductor device of claim 3, wherein the gate electrode is of a trench type.

8. The semiconductor device of claim 3, wherein the recess portion is formed under the emitter region.

9. The semiconductor device of claim 4, wherein the recess portion is not formed in a circumference portion of the semiconductor substrate.

10. The semiconductor device of claim 1, wherein an insulation film is formed on a sidewall of the recess portion.

11. The semiconductor device of claim 3, wherein the current flow is configured to be formed from the emitter electrode to the collector electrode through the base region and a side surface of the recess portion is formed.

12. The semiconductor device of claim 1, further comprising a terminal formed on the front surface of the semiconductor substrate and configured to lead a current from the back surface electrode, and an additional recess portion formed from the back surface toward the front surface, wherein the recess portion is disposed under the MOS structure and the additional recess portion is disposed under the terminal, and the additional recess portion is deeper than the recess portion.

13. The semiconductor device of claim 12, wherein the recess portion has a larger diameter than the recess portion.

14. The semiconductor device of claim 12, wherein the additional recess portion extends so as to contact the terminal.

15. A method of manufacturing a semiconductor device, comprising:

forming a MOS structure on a front surface of a semiconductor substrate of a first general conductivity type;

forming a photoresist pattern on a back surface of the semiconductor substrate;

forming a recess portion by etching the semiconductor substrate using the photoresist pattern as a mask; and

forming a back surface electrode in the recess portion.

16. The method of claim 15, further comprising forming a collector region at a bottom of the recess portion by implanting an impurity of a second general conductivity type.

17. The method of claim 15, wherein the back surface electrode comprises polysilicon.

18. The method of claim 15, wherein the recess portion is not formed in a circumference portion of the semiconductor substrate.

19. The method of claim 15, further comprising forming a terminal on the front surface of the semiconductor substrate and forming an additional recess portion under the terminal, the additional recess portion being formed from the back surface to the front surface and larger than the recess portion that is under the MOS structure.

20. The method of claim 19, wherein the recess portion is formed so as to extend to the terminal so as to contact the terminal.