Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors

• US 20070215954A1
• Filed: 03/16/2006
• Published: 09/20/2007
• Est. Priority Date: 03/16/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Mouli, Chandra
• Granted Patent: US 7,439,594 B2
• Time in Patent Office: Days
• US Class Current: 257/390
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/3148 Silicon Carbide layers
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.

Claims

1. A stacked non-volatile thin film memory device comprising:

a plurality of thin film memory cells stacked vertically on a substrate, each memory cell comprising;

an insulation layer formed over the substrate;

a channel region layer formed over the insulation layer, the channel region layer comprising amorphous silicon layer having a predetermined concentration of carbon;

a dielectric stack formed over the channel region layer; and

a control gate formed over the dielectric stack.

2. The device of claim 1 wherein the control gate is comprised of one of polysilicon or metal.

3. The device of claim 2 wherein the metal is one of TiN or TaN.

4. The device of claim 1 wherein the insulation layer is an oxide layer.

5. The device of claim 1 and further including an insulation material formed vertically between each memory cell.

6. The device of claim 1 wherein the predetermined concentration of carbon is such that the amorphous silicon layer is a silicon carbide layer.

7. The device of claim 1 and further including a pair of source/drain regions formed in the channel region layer on either side of the dielectric stack.

8. A stacked non-volatile thin film memory device comprising:

a plurality of thin film memory cells stacked vertically on a silicon substrate, each memory cell layer comprising;

an oxide layer formed over the substrate;

an amorphous silicon layer formed over the oxide layer and having a predetermined concentration of carbon;

a dielectric stack formed over the channel region layer;

a pair of source/drain regions formed in the amorphous silicon layer on opposing sides of the dielectric stack; and

a control gate formed over the dielectric stack.

9. The device of claim 8 wherein the non-volatile thin film memory device is a flash memory device.

10. The device of claim 8 wherein the predetermined concentration of carbon decreases with each layer of memory cells.

11. The device of claim 8 wherein the dielectric stack comprises an oxide-nitride-oxide structure.

12. The device of claim 8 and further including spacer material formed on opposing sides of the dielectric stack.

13. The device of claim 8 and further including a metal contact formed on each source/drain region in a top layer of the plurality of stack memory cells.

14. A method for fabricating a non-volatile memory device comprising a plurality of layers of vertically stacked thin film memory cells over a substrate, the method for fabricating each layer comprising:

forming an insulation layer;

forming an amorphous silicon film over the insulation layer;

increasing a carbon content in the amorphous silicon film to form a carbon rich silicon film;

forming a dielectric stack over the amorphous silicon layer; and

forming a control gate over the dielectric stack.

15. The method of claim 14 wherein forming the dielectric layer comprises forming an oxide-nitride-oxide layer.

16. The method of claim 14 wherein forming the dielectric layer comprises forming an oxide-high-k dielectric-oxide layer.

17. The method of claim 16 wherein the high-k dielectric comprises one of Al₂O₃, HfO₂, LaO₃, or LaAlO₃.

18. The method of claim 14 wherein forming the control gate comprises forming a metal layer over the dielectric stack.

19. The method of claim 18 wherein the metal layer is comprised of one of TiN or TaN.

20. The method of claim 14 and further including forming spacers on opposing sides of the dielectric stack.

21. The method of claim 14 wherein increasing the carbon content comprises tuning the carbon concentration by controlling Si:

C growth temperature.

22. The method of claim 14 and further including forming an amorphous silicon cap layer between the carbon rich silicon film and the dielectric stack.

23. The method of claim 14 wherein increasing the carbon content comprises increasing the carbon content of the amorphous silicon film such that a lowest layer has a greater carbon content than a higher layer.

24. The method of claim 14 wherein increasing the carbon content comprises introducing less carbon in the amorphous silicon film of each layer as the layers increase.

25. The method of claim 14 and further including forming source/drain regions on opposing sides of the dielectric stack in the carbon rich film.

26. The method of claim 25 wherein the source/drain regions are formed by one of implantation, solid-source diffusion, or plasma doping.

27. The method of claim 14 and further including forming source/drain contacts on the carbon rich silicon film with metal low Schottky barrier contacts.

28. The method of claim 14 and further including forming source/drain contacts in the carbon rich silicon film by gate-induced tunneling through Schottky barriers.

29. The method of claim 14 wherein the dielectric stack is comprised of graded stoichiometry.

30. The method of claim 14 and further including forming an oxide layer between each layer of thin film memory cells.

31. The method of claim 14 wherein the carbon rich silicon film comprises a channel region and the channel region is “

U”

shaped.

32. A stacked non-volatile thin film memory device comprising:

a plurality of thin film FinFET memory cells stacked vertically on a substrate, each memory cell layer comprising;

a pair of source/drain regions formed vertically on the substrate;

a channel region formed vertically over the substrate and between the pair of vertical source/drain regions, the channel region layer comprising amorphous silicon having a predetermined concentration of carbon;

a dielectric stack formed around the channel region; and

a control gate formed around the dielectric stack.

33. The device of claim 32 and further including an oxide layer formed between the dielectric stack and the control gate.

34. The device of claim 32 wherein the control gate is formed as a double gate structure.

35. The device of claim 32 wherein the control gate is formed as a triple gate structure.

36. The device of claim 33 wherein a thickness of the oxide layer determines whether the control gate is a double control gate or a triple control gate.

37. The device of claim 36 wherein the oxide layer on the top of the channel region is thinner than the sidewalls for the double control gate.

38. The device of claim 36 wherein the oxide layer is substantially of equal thickness for the triple control gate.

39. A method for fabricating a stacked non-volatile thin film memory device, the method comprising:

forming a plurality of thin film FinFET memory cell layers stacked vertically on a substrate, the method for forming each memory cell layer comprising;

forming a pair of source/drain regions vertically on the substrate;

forming a channel region of amorphous silicon film vertically over the substrate and between the pair of vertical source/drain regions;

increasing a carbon content in the amorphous silicon film to form a carbon rich silicon film;

forming a dielectric stack around the channel region; and

forming a control gate around the dielectric stack.

40. The method of claim 39 wherein increasing the carbon content comprises increasing the carbon content at a lesser percentage for each subsequently formed vertically stacked thin film FinFET memory cell layer.

41. An memory system comprising:

a processor that generates control signals; and

a memory device coupled to the processor, the device having a memory array comprising a plurality of layers of thin film memory cells formed over a substrate, each layer comprising;

an insulation layer formed over the substrate;

a channel region layer formed over the insulation layer, the channel region layer comprising an amorphous silicon layer having a predetermined concentration of carbon;

a dielectric stack formed over the channel region layer; and

a control gate formed over the dielectric stack.

42. The system of claim 41 and further including a pair of source/drain regions formed in the channel region layer on opposing sides of the dielectric stack.

43. The system of claim 41 wherein the predetermined concentration of carbon decreases in each subsequently formed layer of thin film memory cells.

44. The system of claim 41 wherein the memory array is comprised of a NAND-type architecture.

45. The system of claim 41 wherein the memory array is comprised of a NOR-type architecture.

46. A memory module comprising:

at least two memory devices, each comprising a memory array having a plurality of layers of thin film memory cells formed over a substrate, each layer comprising;

an insulation layer formed over the substrate;

a channel region layer formed over the insulation layer, the channel region layer comprising an amorphous silicon layer having a predetermined concentration of carbon;

a dielectric stack formed over the channel region layer; and

a control gate formed over the dielectric stack; and

a plurality of contacts configured to provide selective contact between the memory array and a host system.

47. The module of claim 46 and further including a memory controller coupled to the memory array for controlling operation of the memory device in response to the host system.

48. A memory module comprising:

a memory device comprising a memory array having a plurality of layers of thin film memory cells formed over a substrate, each layer comprising;

an insulation layer formed over the substrate;

a channel region layer formed over the insulation layer, the channel region layer comprising an amorphous silicon layer having a predetermined concentration of carbon;

a dielectric stack formed over the channel region layer; and

a control gate formed over the dielectric stack;

a housing for enclosing the memory device; and

a plurality of contacts coupled to the housing and configured to provide selective contact between the memory array and a host system.