Integrated passive device substrates

• US 20070215976A1
• Filed: 03/17/2006
• Published: 09/20/2007
• Est. Priority Date: 03/17/2006
• Status: Active Grant

• Current Assignee: Sychip Incorporated (Murata Manufacturing Co Limited)
• Original Assignee: Sychip Incorporated (Murata Manufacturing Co Limited)
• Inventors: Sun, Kunquan, Lau, Maureen, Degani, Yinon, Sun, Liguo, Fan, Yu, Gao, Charley
• Granted Patent: US 7,936,043 B2
• Time in Patent Office: Days
• US Class Current: 257/528
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/19011 including integrated passive components
• CPC Class Codes: H01L 2924/19103 interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive

Abstract

The specification describes an integrated passive device (IPD) that is formed on a silicon substrate covered with an oxide layer. Unwanted accumulated charge at the silicon/oxide interface are rendered immobile by creating trapping centers in the silicon surface. The trapping centers are produced by a polysilicon layer interposed between the silicon substrate and the oxide layer.

Claims

1. A method for fabricating an integrated passive device (IPD) comprising the steps of:

a. providing a silicon wafer substrate, the silicon wafer substrate having intrinsic conductivity, and having a plurality of IPD sites,

b. forming a polysilicon layer on the silicon wafer substrate.

c. forming an insulating layer on the polysilicon layer, and

b. forming at least one thin film passive device on the IPD sites.

2. The method of claim 1 wherein the silicon wafer substrate has a resistivity of more than 0.1 KOhm-cm.

3. The method of claim 1 wherein the polysilicon layer has a resistivity of more than 0.1 KOhm-cm.

4. The method of claim 3 wherein the polysilicon layer has a thickness greater than 0.1 microns.

5. The method of claim 4 wherein the polysilicon layer is deposited on the silicon wafer using CVD.

6. The method of claim 1 wherein the silicon wafer substrate has a resistivity of more than 1.0 KOhm-cm.

7. The method of claim 3 wherein the single crystal silicon wafer has a diameter of at least 8 inches.

8. The method of claim 1 wherein the thin film passive device comprises one or more inductors.

9. An integrated passive device (IPD) comprising:

a. a silicon wafer substrate, the silicon wafer substrate having intrinsic conductivity, and having a plurality of IPD sites,

b. a polysilicon layer on the silicon wafer substrate,

c. an insulating layer on the polysilicon layer, and

b. at least one thin film passive device on the IPD sites.

10. The IPD of claim 9 wherein the silicon wafer substrate has a resistivity of more than 0.1 KOhm-cm.

11. The IPD of claim 10 wherein the polysilicon layer has a resistivity of more than 0.1 KOhm-cm.

12. The IPD of claim 11 wherein the polysilicon layer has a thickness greater than 0.1 microns.

13. The IPD of claim 9 wherein the silicon wafer substrate has a resistivity of more than 1.0 KOhm-cm.

14. The IPD of claim 9 wherein the single crystal silicon wafer has a diameter of at least 8 inches.

15. The IPD of claim 9 wherein the thin film passive device comprises one or more inductors.

16. The IPD of claim 9 comprising a plurality of inductors, and a plurality of passive resistor and/or capacitor devices.

17. A substrate comprising a planar silicon wafer, a planar layer of polysilicon on the wafer, and an insulating layer on the layer of polysilicon.