DC current regulator insensitive to conducted EMI

• US 20070216484A1
• Filed: 01/10/2007
• Published: 09/20/2007
• Est. Priority Date: 01/10/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Steyaert, Michiel, Redoute, Jean-Michel
• Granted Patent: US 7,427,854 B2
• Time in Patent Office: Days
• US Class Current: 330/257
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

A DC current regulator circuit comprises a first circuit node (32) which is operable to receive an external input voltage. A transistor (M1) has an input, a first leg and a second leg. The first leg of the transistor is isolated from the first circuit node (32). An amplifier (10) has an output connected to the input of the transistor (M1), a first amplifier input for receiving a reference voltage (VREF) and a second amplifier input connected to the first circuit node (32). A low-pass filter (33) connects between the output of the amplifier and the first circuit node (32). A current mirror (36) connects in series with the second leg of the transistor (M1) and has a first branch (38) for providing a regulated output current and a second branch (37) which connects to the first circuit node (32). The current regulator has reduced sensitivity to conducted EMI received at the first circuit node (32).

Claims

1. A current regulator circuit comprising:

a first circuit node (32) which is operable to receive an external input voltage;

a transistor (M1) having an input, a first leg and a second leg, the first leg of the transistor being isolated from the first circuit node (32);

an amplifier (10) having an output connected to the input of the transistor, a first amplifier input for receiving a reference voltage (VREF) and a second amplifier input connected to the first circuit node (32);

a low-pass filter (33) connected between the output of the amplifier and the first circuit node (32);

a current mirror (36) connected in series with the second leg of the transistor (M1) and having a first branch (38) for providing a regulated output current and a second branch (37) which connects to the first circuit node (32), wherein the first branch (38) is directly or indirectly coupled to an output stage (40), which comprises a further current mirror, wherein the further current mirror is an EMI-filtering current mirror.

2. A current regulator circuit according to claim 1 wherein the low-pass filter (33) is an integrator comprising a resistor (Ri) connected between the first circuit node (32) and the second input of the amplifier (10) and a capacitor (Ci) connected between the output of the amplifier (10) and the second input of the amplifier (10).

3. A current regulator circuit according to claim 1 wherein the low-pass filter (33) has a bandwidth such that the gain-bandwidth product (GBW) of the amplifier is lower than a predetermined EMI frequency.

4. A current regulator according to claim 3, wherein the predetermined EMI frequency is the lowest EMI frequency to be filtered.

5. A current regulator circuit according to claim 3 wherein the low-pass filter (33) has a bandwidth such that the gain-bandwidth product (GBW) of the amplifier is at least one order of magnitude lower than the lowest EMI frequency to be filtered.

6. A current regulator circuit according to claim 5 wherein the low-pass filter (33) has a bandwidth such that the gain-bandwidth product (GBW) of the amplifier is at least two orders of magnitude lower than the lowest EMI frequency to be filtered.

7. A current regulator circuit according to claim 1 wherein the first leg of the transistor (M1) connects to a supply rail via a resistor (34) which is operable to self-bias the transistor (M1).

8. A current regulator circuit according to claim 1, wherein the EMI filtering current mirror comprises:

a second transistor (M7) and a third transistor (M10) whose gates are connected together at a mirror node (43), the second transistor (M7) having an input branch (41) to receive current and the third transistor (M10) having an output branch (42) to mirror the received current as an output current (I_ref);

a fourth transistor (M8) connected between the mirror node (43) and a supply rail (Vcc); and

,

a fifth transistor (M9) connected between the mirror node (43) and another supply rail and having an input connected to the input branch.

9. A current regulator circuit according to claim 8 further comprising a first capacitor connected between the input branch and a supply rail (Vcc) and a second capacitor connected between the mirror node (43) and the supply rail (Vcc).

12. A method of generating a regulated current using the current regulator circuit according to claim 1.

13. A method of generating a regulated current using the current regulator circuit according to claim 8.

17. A current regulator circuit according to claim 1 implemented in the form of an integrated circuit, where the first circuit node connects to an external pin of the integrated circuit.

18. A current regulator circuit according to claim 8 implemented in the form of an integrated circuit, where the first circuit node connects to an external pin of the integrated circuit.

10. A current regulator circuit comprising:

a first circuit node which is operable to receive an external input voltage;

a transistor having an input, a first leg and a second leg, the first leg of the transistor being connected to the first circuit node;

an amplifier (10) having an output connected to the input of the transistor, a first amplifier input for receiving a reference voltage (VREF) and a second amplifier input connected to the first circuit node;

a low-pass filter connected between the output of the amplifier and the first circuit node; and

,

a current mirror connected in series with the second leg of the transistor, wherein the current mirror comprises a second transistor and a third transistor whose gates are connected together at a mirror node, the third transistor having an input branch connected in series with the second leg of the transistor to receive current and the third transistor having an output branch to mirror the received current as an output current (I_ref);

a fourth transistor connected between the mirror node and a supply rail (Vcc); and

,

a fifth transistor connected between the mirror node and another supply rail and having an input connected to the input branch.

11. A current regulator circuit according to claim 10 further comprising a first capacitor connected between the input branch and a supply rail and a second capacitor connected between the mirror node and the supply rail.

14. A method of generating a regulated current using the current regulator circuit according to claim 10.

19. A current regulator circuit according to claim 10 implemented in the form of an integrated circuit, where the first circuit node connects to an external pin of the integrated circuit.

15. A current mirror circuit comprising:

a first transistor (M7) and a second transistor (M10) whose gates are connected together at a mirror node (43), the first transistor (M7) having an input branch (41) to receive current and the second transistor (M10) having an output branch (42) to mirror the received current as an output current (I_ref);

a third transistor (M8) connected between the mirror node (43) and a supply rail (Vcc); and

,

a fourth transistor (M9) connected between the mirror node (43) and another supply rail and having an input connected to the input branch.

16. A current mirror circuit according to claim 15 further comprising a first capacitor connected between the input branch and a supply rail (Vcc) and a second capacitor connected between the mirror node (43) and the supply rail (Vcc).

20. A current regulator circuit according to claim 15 implemented in the form of an integrated circuit, where the first circuit node connects to an external pin of the integrated circuit.