THIN FILM TRANSISTOR ARRAY PANEL AND A LIQUID CRYSTAL DISPLAY INCLUDING THE SAME

• US 20070216627A1
• Filed: 04/24/2007
• Published: 09/20/2007
• Est. Priority Date: 07/08/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Byeong-Seob Ban, Jong-Lae Kim, Joon-Hak Oh, So-Youn Park
• Inventors: Oh, Joon-Hak, Park, So-Youn, Kim, Jong-Lae, Ban, Byeong-Seob
• Granted Patent: US 7,733,434 B2
• Time in Patent Office: Days
• US Class Current: 345/92
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A thin film transistor array panel is provided, which includes: a substrate; a plurality of first signal lines formed on the substrate; a plurality of second signal lines intersecting, and intersection from, the first signal lines; a plurality of pixel electrodes formed in insulated areas of the first and second signal lines; a plurality of first thin film transistors electrically connected to the first signal lines, the second signal lines, and the pixel electrodes; a plurality of buffer electrodes capacitively coupled to the pixel electrodes and located at a boundary of the intersection areas; and a plurality of second thin film transistors electrically connected to the buffer electrodes and the first signal lines, wherein the first signal lines are connected to the pixel electrodes of a previous row.

Claims

1. A liquid crystal display, comprising:

a thin film transistor array panel;

a common electrode panel including a common electrode and facing the thin film transistor array panel;

a liquid crystal layer disposed between the thin film transistor array panel and the common electrode panel;

wherein the thin film transistor array panel, comprises;

a substrate, first signal lines formed on the substrate, second signal lines intersecting, and insulated from, the first signal lines;

pixel electrodes formed in intersection areas of the first and second signal lines;

first thin film transistors electrically connected to the first signal lines, the second signal lines, and the pixel electrodes; and

buffer electrodes being supplied with a first voltage higher than a second voltage of the pixel electrodes with the respect to a common voltage of the common electrode and located at a boundary of the intersection areas.

2. The liquid crystal display of claim 1, further comprising:

a first alignment layer formed on the thin film transistor array panel; and

a second alignment layer formed on the common electrode panel,

wherein the first and the second alignment layers are rubbed in the same direction.

3. The liquid crystal display of claim 2, wherein the first and the second alignment layers are homogenous.

4. The liquid crystal display of claim 2, wherein the liquid crystal molecules of the liquid crystal layer have a symmetrical alignment with respect to the center between the thin film transistor array panel and the common electrode panel.

5. The liquid crystal display of claim 4, wherein the liquid crystal molecules of the liquid crystal layer have a bend arrangement.

6. The liquid crystal display of claim 1, wherein the liquid crystal molecules of the liquid crystal layer are driven with a voltage equal to or higher than a threshold voltage to display images.

7. The liquid crystal display of claim 1, wherein the buffer electrodes are capacitively coupled to the pixel electrodes.

8. The liquid crystal display of claim 7, further comprising:

a plurality of second thin film transistors electrically connected to the buffer electrodes and the first signal lines,

wherein the first signal lines are electrically connected to the pixel electrodes of a previous row.

9. The liquid crystal display of claim 8, further comprising:

coupling electrodes connected to the pixel electrodes, the coupling electrodes overlapping, and insulated from, the buffer electrodes.

10. The liquid crystal display of claim 9, wherein the coupling electrodes are connected to drain electrodes of the first thin film transistors.

11. The liquid crystal display of claim 7, further comprising:

a plurality of third signal lines intersecting the second signal lines,

wherein one of the terminals of the second thin film transistors is connected to the third signal lines.

12. The liquid crystal display of claim 11, wherein the pixel electrodes and the buffer electrodes are located on the same layer.

13. The liquid crystal display of claim 1, wherein the buffer electrodes overlap the first signal line.