Digital-to-analog converter and method of digital-to-analog conversion

• US 20070216633A1
• Filed: 03/07/2007
• Published: 09/20/2007
• Est. Priority Date: 03/16/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Hyung-Tae
• Granted Patent: US 8,013,769 B2
• Time in Patent Office: Days
• US Class Current: 345/100
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2320/0276 for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• CPC Class Codes: H03M 1/76 using switching tree
• CPC Class Codes: H03M 1/806 with equally weighted capacitors which are switched by unary decoded digital signals

Abstract

In one embodiment, the DAC includes an analog gray voltage generation unit configured to generate a plurality of analog gray voltages, and a first decoder configured to select two different voltages of the plurality of the gray voltages as a first level voltage and a second level voltage, respectively, in response to an upper K-bits of N-bit input image data. Here, N may be an integer not less than two, and K may be an integer less than N. A second decoder may be configured to repeatedly distribute the first level voltage and the second level voltage to output a plurality of distributed voltages in response to a lower L-bits of the N-bit input image data. Here, L may be equal to N subtracted by K, and L may be less than K. An interpolated voltage generation unit may be configured to generate an interpolated voltage based on the plurality of distributed voltages.

Claims

1. A digital-to-analog converter (DAC) comprising:

an analog gray voltage generation unit configured to generate a plurality of analog gray voltages;

a first decoder configured to select two different voltages of the plurality of the gray voltages as a first level voltage and a second level voltage, respectively, in response to an upper K-bits of N-bit input image data, N being an integer not less than two, K being an integer less than N;

a second decoder configured to repeatedly distribute the first level voltage and the second level voltage to output a plurality of distributed voltages in response to a lower L-bits of the N-bit input image data, L being equal to N subtracted by K, L being less than K; and

an interpolated voltage generation unit configured to generate an interpolated voltage based on the plurality of distributed voltages.

2. The DAC of claim 1, wherein the plurality of analog voltages corresponds in number to a number of logic combinations of the upper K-bits of the N-bit input image data.

3. The DAC of claim 1, wherein the second decoder repeats the first level voltage P times and repeats the second level voltages Q-P times to generate the distributed voltages, where Q corresponds to a number of the distributed voltages, and P is an integer not less than one and not greater than Q.

4. The DAC of claim 1, wherein the second decoder is configured to set a value of P based on the lower L-bits of the N-bit input image data.

5. The DAC of claim 4, wherein for L=2, there are four possible sets of the plurality of distributed voltages, each set corresponding to one of P=4, 3, 2, and 1.

6. The DAC of claim 4, wherein for L=2, the second decoder is configured to output one of the following sets of four voltages as the plurality of distributed voltages:

(Vh, Vh, Vh, Vh), (Vh, Vh, Vh, VI), (Vh, Vh, VI, VI), (Vh, VI, VI, VI) in response to the lower 2-bits of the N-bit input image data, where Vh represents the first level voltage and VI represents the second level voltage.

7. The DAC of claim 6, wherein the interpolated voltage generation unit is configured to generate the interpolated voltage to have a level corresponding to one of Vh, (3Vh+I)/4, (Vh+VI)/2, and (Vh+3VI)/4.

8. The DAC of claim 4, wherein for L=1, these are two possible sets of the plurality of distributed voltages, each set corresponding to one of P=2 and 1.

9. The DAC of claim 4, wherein for L=1, the second decoder is configured to output one of the following sets of two voltages as the plurality of distributed voltages:

(Vh, Vh), (Vh, VI) in response to the lower 1-bit of N-bit input image data, where Vh represents the first level voltage and VI represents the second level voltage.

10. The DAC of claim 9, wherein the interpolated voltage generation unit is configured to generate the interpolated voltage to have a level corresponding to one of Vh, and (Vh+VI)/2.

11. The DAC of claim 1, wherein the interpolated voltage generation unit is implemented with an auto-zero sample-and-hold circuit.

12. The DAC of claim 1, wherein the interpolated voltage generation unit is configured to generate the interpolated voltage as an average of the plurality of distributed voltages.

13. The DAC of claim 12, wherein the interpolated voltage generation unit comprises:

an amplifier;

a capacitor unit connected to an input terminal of the amplifier;

a first switching unit configured to selectively supply the plurality of distributed voltages to the capacitor unit;

a second switching unit configured to selectively connect an output terminal of the amplifier with the input terminal of the amplifier; and

a third switching unit configured to selectively connect the terminals of the capacitor unit and the output terminal of the amplifier.

14. The DAC of claim 13, wherein the interpolated voltage generation unit further comprises:

a fourth switching unit configured to selectively connect the output terminal of the amplifier with an external device.

15. The DAC of claim 13, wherein the interpolated voltage generation unit charges the capacitor unit with the plurality of distributed voltages to sample the plurality of distributed voltages by simultaneously turning on the first switching unit and the second switching unit, and averages the plurality of distributed voltages by simultaneously turning off the first switching unit and the second switching unit and turning on the third switching unit.

16. The DAC of claim 13, wherein the second switching unit and the third switching unit set a self-offset of the amplifier to substantially zero through their switching operations.

17. A method of digital-to-analog (DA) conversion comprising:

generating a plurality of analog gray voltages;

selecting two different voltages of the plurality of the gray voltages as a first level voltage and a second level voltage in response to an upper K-bits of N-bit input image data, N being an integer not less than two, K being an integer less than N;

distributing the first level voltage and the second level voltage repeatedly to generate a plurality of distributed voltages in response to a lower L-bits of the N-bit input image data, L being equal to N subtracted by K, and L being less than K; and

averaging the plurality of distributed voltages to output an interpolated voltage.

18. The method of claim 17, wherein the averaging step comprises:

storing the plurality of distributed voltages in a capacitor unit as a configuration of charges;

averaging the plurality of distributed voltages by short-circuiting capacitors included in the capacitor unit; and

outputting the average as the interpolated voltage.

19. The method of claim 17, wherein the distributing step repeats the first level voltage P times and repeats the second level voltages Q-P times to generate the distributed voltages, where Q corresponds to a number of the distributed voltages, and P is an integer not less than one and not greater than Q.

20. The method of claim 17, wherein for L=2, the distributing step is configured to output one of the following sets of four voltages as the plurality of distributed voltages:

(Vh, Vh, Vh, Vh), (Vh, Vh, Vh, VI), (Vh, Vh, VI, VI), (Vh, VI, VI, VI) in response to the lower 2-bits of the N-bit input image data, where Vh represents the first level voltage and VI represents the second level voltage.

21. The method of claim 20, wherein the interpolated voltage has a voltage level corresponding to one of Vh, (3Vh+1)/4, (Vh+VI)/2, and (Vh+3VI)/4.

22. The method of claim 17, wherein for L=1, the distributing step is configured to output one of the following sets of two voltages as the plurality of distributed voltages:

(Vh, Vh), (Vh, VI) in response to the lower 1-bit of the N-bit input image data, where Vh represents the first level voltage and VI represents the second level voltage.

23. The method of claim 22, wherein the interpolated voltage has a voltage level corresponding to one of Vh, and (Vh+VI)/2.

24. The method of claim 17, wherein the generating step generates the plurality of analog gray voltages such that a number of the analog gray voltages corresponds to a number of logic combinations of the upper K-bits of the N-bit input image data.