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MEMORY ARRAY INCORPORATING MEMORY CELLS ARRANGED IN NAND STRINGS

  • US 20070217263A1
  • Filed: 05/21/2007
  • Published: 09/20/2007
  • Est. Priority Date: 12/05/2003
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • a memory array having at least two planes of memory cells formed above a substrate, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof;

    wherein each respective NAND string within a given memory block of a given memory plane is coupled to a respective global bit line that is not shared by other NAND strings within the given memory block of the given memory plane, and wherein some adjacent NAND strings within a memory block are coupled at opposite ends thereof to their respective global bit lines.

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