Photo-masking method for fabricating TFT array substrate

• US 20070218581A1
• Filed: 03/19/2007
• Published: 09/20/2007
• Est. Priority Date: 03/17/2006
• Status: Active Grant

• Current Assignee: InnoLux Corporation
• Original Assignee: Innolux Display Corporation (InnoLux Corporation)
• Inventors: Fu, Jian-Jhong
• Granted Patent: US 7,989,142 B2
• Time in Patent Office: Days
• US Class Current: 438/48
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

An exemplary method for fabricating a TFT array substrate includes providing an insulating substrate (201); coating a gate metal layer (202) on the substrate; forming a plurality of gate electrodes (212) using a first photo-mask process; forming a gate insulating layer (203), a semiconducting layer (205), and a source/drain metal layer (206) on the substrate having the gate electrodes; forming a plurality of source electrodes (217) and a plurality of drain electrodes (218) using a second photo-mask process; forming a passivation material layer (209) and a photo resist layer on the gate insulating layer, the source electrodes and the drain electrodes; forming a passivation layer (219) and the photo resist pattern (234) using a third photo-mask process; forming a transparent conductive metal layer (204) on the photo resist pattern, the drain electrode and the gate insulating layer; and forming a pixel electrode (214) through removing the photo resist pattern.

Claims

1. A method for fabricating a thin film transistor (TFT) array substrate, the method comprising:

providing an insulating substrate;

coating a gate metal layer on the substrate;

forming a plurality of gate electrodes using a first photo-mask process;

forming a gate insulating layer, a semiconducting layer, and a source/drain metal layer on the substrate having the gate electrodes;

forming a plurality of source electrodes and a plurality of drain electrodes using a second photo-mask process, each of pairs of one source electrode and one drain electrode defining a channel therebetween;

Forming a passivation material layer and a photo resist layer on the gate insulating layer, the source electrodes and the drain electrodes;

forming a passivation layer and the photo resist pattern using a third photo-mask process;

forming a transparent conductive metal layer on the photo resist pattern, the drain electrode and the gate insulating layer; and

forming a pixel electrode through removing the photo resist pattern.

2. The method as claimed in claim 1, wherein the second photo-mask process comprises coating a photo-resist layer on the source/drain metal layer, exposing the photo-resist layer using a photo-mask having a plurality of slits, and developing the exposed photo-resist layer to form a photo-resist pattern.

3. The method as claimed in claim 2, wherein the photo-resist pattern has a plurality of grooves.

4. The method as claimed in claim 3, wherein the second photo-mask process further comprises etching the photo-resist layer beneath the grooves, thereby exposing a portion of the source/drain metal layer corresponding to the groove.

5. The method as claimed in claim 2, wherein the second photo-mask process further comprises etching the source/drain metal layer and the semiconducting layer, thereby forming the source/drain metal layer pattern and the semiconducting layer pattern.

6. The method as claimed in claim 1, wherein the second photo-mask process further comprises depositing a photo-resist layer and utilizes a light diffraction technique to expose and develop the photo-resist layer.

7. The method as claimed in claim 1, wherein the second photo-mask process further comprises depositing a photo-resist layer and utilizes a photo-mask having transparent portions, opaque portions and semitransparent portions to expose the second photo-resist layer to produce the second photo-resist pattern having the groove.

8. The method as claimed in claim 1, wherein the first photo-mask process comprises depositing a photo-resist layer on the gate metal layer and exposing the photo-resist layer by a photo-mask.

9. The method as claimed in claim 1, wherein the first photo-mask process comprises etching the gate metal layer and removing residual photo-resist layer.

10. The method as claimed in claim 1, wherein the process of forming a plurality of gate electrodes further comprises forming a common line at the same time.

11. The method as claimed in claim 1, wherein the substrate is made from glass or quartz.

12. The method as claimed in claim 1, wherein the transparent conductive layer is made from indium tin oxide or indium zinc oxide.

13. The method as claimed in claim 1, wherein the gate metal layer is made from material including any one or more items selected from the group consisting of aluminum, molybdenum, copper, chromium, and tantalum.

14. The method as claimed in claim 1, wherein the source/drain metal layer is made from material including any one or more items selected from the group consisting of aluminum, aluminum alloy, molybdenum, tantalum, and molybdenum-tungsten alloy.

15. A TFT array substrate comprising:

an insulative substrate;

a gate electrode and a common line formed on the substrate and spaced from each other;

a gate insulating layer formed on said substrate, said gate electrode and the common line in a staggered manner;

a semiconducting layer pattern formed on a portion of the gate insulating layer with a dish-like cross-section;

a source electrode and a drain electrode being formed on two upper side corners of the semiconducting layer pattern;

a passivation layer pattern formed on all the source electrode and on a middle portion of the semiconducting layer pattern between said two upper side corners, and a little portion of the drain electrode; and

a pixel electrode formed on the rest of the gate insulating layer and the rest of the drain electrode.