METHOD FOR FABRICATING A RECESSED-GATE MOS TRANSISTOR DEVICE

• US 20070218612A1
• Filed: 12/27/2006
• Published: 09/20/2007
• Est. Priority Date: 03/15/2006
• Status: Abandoned Application

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Lin, Shian-Jyh, Cheng, Chien-Li
• Application Number:
  US11/616,298
• Publication Number:
  US 20070218612A1
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A method for fabricating a recessed-gate transistor is disclosed. A trench is recessed into a substrate. A spacer is formed on sidewalls of the trench. A trench bottom oxide is formed. The spacer is then stripped off. A source/drain doping region is formed on the exposed sidewalls of the trench in a self-aligned fashion. The trench bottom oxide is then stripped, thereby forming a curved trench bottom and smile-shaped gate channel.

Claims

1. A method for fabricating a recessed gate MOS transistor device, comprising:

forming a gate trench in a substrate, wherein said gate trench comprises a trench bottom and trench sidewall;

forming a spacer on said trench sidewall;

forming a trench bottom oxide at said trench bottom;

removing said spacer to reveal said trench sidewall;

forming a source/drain diffusion region on said trench sidewall;

removing said trench bottom oxide to form an arc-shaped trench bottom;

forming a gate dielectric layer on said arc-shaped trench bottom; and

forming a gate material in said gate trench.

2. The method of claim 1 wherein said spacer comprises silicon nitride.

3. The method of claim 2 wherein said spacer has a thickness of 10-500 angstroms.

4. The method of claim 1 wherein said trench bottom oxide is formed by Localized Oxidation of Silicon (LOCOS) process.

5. The method of claim 1 wherein said source/drain diffusion region is formed by Gas-Phase Diffusion (GPD) method.

6. The method of claim 1 wherein said source/drain diffusion region is formed by tilt-angle ion implantation method.

7. The method of claim 1 wherein said gate dielectric layer is formed by In-Situ Steam Growth (ISSG) method.

8. The method of claim 1 wherein said gate material comprises doped polysilicon.

9. The method of claim 1 wherein before forming said gate dielectric layer on said arc-shaped trench bottom, the method further comprises:

forming a sacrificing oxide layer on said trench sidewall and said arc-shaped trench bottom; and

performing a dry etching process to etch the sacrificing oxide layer thereby revealing the arc-shaped trench bottom.