Method of fabricating local interconnects on a silicon-germanium 3D CMOS

• US 20070218622A1
• Filed: 03/15/2006
• Published: 09/20/2007
• Est. Priority Date: 03/15/2006
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Maa, Jer-Shen, Lee, Jong-Jan, Hsu, Sheng, Schuele, Paul
• Granted Patent: US 7,378,309 B2
• Time in Patent Office: Days
• US Class Current: 438/231
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

A method of fabricating local interconnect on a silicon-germanium 3D CMOS includes fabricating an active silicon CMOS device on a silicon substrate. An insulator layer is deposited on the silicon substrate and a seed window is opened through the insulator layer to the silicon substrate and to a silicon CMOS device gate. A germanium thin film is deposited on the insulator layer and into windows, forming a contact between the germanium thin film and the silicon device. The germanium thin film is encapsulated in a dielectric material. The wafer is heated at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition. The wafer is cooled to solidify the germanium as single crystal germanium and as polycrystalline germanium, which provides local interconnects. Germanium CMOS devices may be fabricated on the single crystal germanium thin film.

Claims

1. A method of fabricating local interconnect on a silicon-germanium 3D CMOS comprising:

fabricating an active silicon CMOS device, having a gate, on a silicon substrate;

depositing an insulator layer on the silicon substrate;

opening a seed window through the insulator layer to the silicon substrate and to the gate of the silicon CMOS device;

depositing a germanium thin film on the insulator layer, wherein the germanium fills the windows forming a contact between the germanium thin film and the silicon substrate, and between the germanium thin film and the silicon CMOS device;

patterning and etching the germanium thin film;

encapsulating the germanium thin film in a dielectric material;

rapid thermal annealing the wafer and the layers formed thereon at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition;

cooling to solidify the germanium as single crystal germanium and as polycrystalline germanium;

fabricating a germanium CMOS on the single crystal germanium thin film; and

using germanium taken from the forms of germanium consisting of single crystal germanium and polycrystalline germanium to from local interconnects between the silicon CMOS and the germanium CMOS.

2. The method of claim 1 wherein said rapid thermal annealing includes rapidly heating at a target temperature of between about 920°

C. to 1000°

C., and annealing at the target temperature for between about zero seconds and sixty seconds.

3. The method of claim 1 wherein said depositing a germanium thin film on the insulator layer includes depositing a germanium layer taken from the group of germanium materials consisting of polygermanium and amorphous germanium.

4. The method of claim 1 wherein the seed window provides for a germanium-to-silicon interface so that a germanium crystallization process begins at the germanium-to-silicon interface and provides electrical contact between germanium-based devices and silicon-based devices.

5. A method of fabricating local interconnect on a silicon-germanium 3D CMOS SRAM cell comprising:

fabricating a silicon gate transistor;

fabricating a silicon NMOS pull down transistor and a silicon NMOS pass gate transistor;

fabricating a germanium-on-insulator thin film by liquid phase epitaxy;

fabricating a germanium PMOS pull up transistor; and

forming a germanium local interconnect to connect the germanium PMOS pull-up transistor, the silicon NMOS pull-down transistor and the silicon NMOS pass gate transistor.

6. The method of claim 5 wherein said fabricating a germanium-on-insulator thin film and said forming a germanium local interconnect include rapid thermal annealing at a temperature sufficient to flow the germanium, while maintaining other materials in a solid condition.

7. The method of claim 6 wherein said rapid thermal annealing includes rapidly heating to a target temperature of between about 920°

C. to 1000°

C., and annealing at the target temperature for between about zero seconds and sixty seconds.

8. The method of claim 5 which includes doping the germanium local interconnect with an n-type dopant taken from the group of n-type dopants consisting of phosphorus or arsenic to reduce the resistance in the germanium local interconnect.

9. The method of claim 5 which includes formation of GeM_x to prevent PN diode formation at the germanium film, wherein M is a metal taken from the group of metals consisting of Ti, Co, Ni and Ta, and where x has a value of between 0.3 to 3.

10. The method of claim 5 wherein the germanium PMOS includes a gate formed of a material taken from the group of materials consisting of n-type polysilicon, n-type polygermanium and n-type polySiGe, and forms a buried channel PMOS transistor, thereby preventing formation of a PN junction at the local interconnect between the germanium PMOS gate, a silicon NMOS gate and a silicon NMOS source/drain.

11. A method of fabricating local interconnect on a silicon-germanium 3D CMOS comprising:

preparing a silicon substrate wafer;

depositing a gate dielectric layer and forming a gate thereon;

fabricating an active silicon CMOS device, having a device gate, on the silicon substrate;

depositing an insulator layer on the silicon substrate;

opening a window through the insulator layer to the silicon substrate and to the device gate;

depositing a germanium thin film on the insulator layer, wherein the germanium fills the windows forming a contact between the germanium thin film and the silicon substrate, and between the germanium thin film and the silicon CMOS device;

patterning and etching the germanium thin film;

encapsulating the germanium thin film with a dielectric material;

annealing the wafer and the layers formed thereon at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition; and

cooling the wafer and the layers formed thereon to provide for liquid phase epitaxy of the germanium to form a single crystal germanium layer and a polycrystalline germanium layer, wherein the single crystal germanium layer is used for subsequent germanium CMOS fabrication and wherein the polycrystalline germanium layer and single crystal germanium layer are used for local interconnects.

12. The method of claim 11 wherein said annealing the wafer includes rapidly heating the wafer to a target temperature of between about 920°

C. to 1000°

C., and annealing the wafer at the target temperature for between about zero seconds and sixty seconds.

13. The method of claim 11 wherein said depositing a germanium thin film on the insulator layer includes depositing a germanium layer taken from the group of germanium materials consisting of polygermanium and amorphous germanium.

14. The method of claim 11 wherein the seed window provides for a germanium-to-silicon interface so that a germanium crystallization process begins at the germanium-to-silicon interface and provides electrical contact between germanium-based devices and silicon-based devices.