Systems and methods for saving power in a digital broadcast receiver

• US 20070218936A1
• Filed: 05/03/2007
• Published: 09/20/2007
• Est. Priority Date: 03/24/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: SiPort, Inc. (Intel Corporation)
• Inventors: Arad, Oren, Waxman, Shay
• Granted Patent: US 7,916,711 B2
• Time in Patent Office: Days
• US Class Current: 455/522
• CPC Class Codes: H04H 20/42 Arrangements for resource management
• CPC Class Codes: H04H 20/426 Receiver side
• CPC Class Codes: H04H 20/72 of terrestrial networks
• CPC Class Codes: H04H 2201/20 digital audio broadcasting [DAB]
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Systems and methods for conserving power in a receiver device are provided. In exemplary embodiments, a receiver device comprises a tuner configured to receive a transmitted signal, at least one analog-to-digital converter (ADC), and a digital signal processing hardware comprising a control logic. The exemplary control logic is configured to determine if a symbol within the transmitted signal belongs to an erasure interval, and generate a control signal to configure a receiver device component to conserve power based on the determination.

Claims

1. A system for power conservation in a receiver device, comprising:

a tuner configured to receive a transmitted signal;

at least one analog-to-digital converter (ADC); and

a digital signal processing hardware (DSPHW) comprising a control logic, the control logic configured to determine if a symbol within the transmitted signal belongs to an erasure interval and generate a control signal to configure a receiver device component to conserve power based on the determination.

2. The system of claim 1 wherein the receiver device component comprises a tuner component.

3. The system of claim 1 wherein the receiver device component comprises a DSPHW component.

4. The system of claim 1 wherein the receiver device component comprises the ADC.

5. The system of claim 1 wherein the DSPHW is further configured to perform clock gating to conserve power in the receiver device.

6. The system of claim 1 wherein the control signal is configured to transition a tuner component between different power modes.

7. The system of claim 1 wherein the DSPHW is further configured to generate a wakeup signal to activate a receiver device component.

8. The system of claim 7, wherein the DSPHW is further configured to determine a wakeup interval.

9. The system of claim 1, wherein the DSPHW is further configured to stream erased bits based on the determination.

10. A method for power conservation in a receiver device, comprising:

receiving a transmitted signal;

determining if a symbol within the transmitted signal belongs to an erasure interval; and

generating a control signal to configure a receiver device component to conserve power based on the determination.

11. The method of claim 10 wherein generating the control signal comprises generating the control signal to conserve the power of a tuner component.

12. The method of claim 10 wherein generating the control signal comprises generating the control signal to conserve the power of a DSPHW component.

13. The method of claim 10 wherein generating the control signal comprises generating the control signal to conserve the power of the ADC.

14. The method of claim 10 further comprising clock gating to conserve power of the receiver device.

15. The method of claim 10 wherein generating the control signal comprises generating the control signal to transition a tuner component between different power modes.

16. The method of claim 10 further comprising generating a wakeup signal to activate a receiver device component.

17. The method of claim 16 further comprising determining a wakeup interval.

18. The method of claim 10 further comprising streaming erased bits based on the determination.

19. A system for power conservation in a receiver device, comprising:

means for receiving a transmitted signal;

means for determining if a symbol within the transmitted signal belongs to an erasure interval; and

means for generating a control signal to configure a receiver device component to conserve power based on the determination.

20. The system of claim 19 further comprising a means for streaming erased bits based on the determination.