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Fault tolerant computing system

  • US 20070220367A1
  • Filed: 02/06/2006
  • Published: 09/20/2007
  • Est. Priority Date: 02/06/2006
  • Status: Abandoned Application
First Claim
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1. A system for tolerating a single event fault in an electronic circuit, comprising:

  • a main processor that controls the operation of the system;

    a fault detection processor responsive to the main processor;

    three or more programmable logic devices responsive to the fault detection processor; and

    wherein the three or more programmable logic devices periodically issue independent input signals to the fault detection processor for determination of one or more single event fault conditions.

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