Fault isolation and availability mechanism for multi-processor system

• US 20070220369A1
• Filed: 02/21/2006
• Published: 09/20/2007
• Est. Priority Date: 02/21/2006
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Fayad, Camil, Sutter, Siegfried, Li, John
• Application Number:
  US11/358,174
• Publication Number:
  US 20070220369A1
• Time in Patent Office: Days
• US Class Current: 714/48
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/181 Eliminating the failing redundant component
• CPC Class Codes: G06F 11/184 where the redundant components implement processing functionality
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

A method and apparatus are provided for identifying a defective processor of a plurality of processors of a multi-processor system. In such method, a first command is submitted to a first processor and to a second processor within the multi-processor system. The first command is executed by each of the first and second processors. A first result of executing the first command by the first processor is compared with a second result of executing the second command by the second processor. A hard error is indicated when the first result does not match the second result. To further isolate a fault within the system, commands are submitted to different pairings of processors and the results are compared to isolate a faulty processor from among them.

Claims

1. A method of identifying a defective processor of a plurality of processors of a multi-processor system, comprising:

(a) submitting a first command to a first processor and a second processor of a plurality of processors within a multi-processor system;

(b) executing the first command by each of the first and second processors;

(c) comparing a first result of executing the first command by the first processor with a second result of executing the second command by the second processor; and

(d) indicating an error when the step of comparing indicates that the first result does not match the second result.

2. The method as claimed in claim 1, further comprising, when the first result, performing a step (e) of repeating a predetermined number of times the sequence of steps (a) though (d) and when said error is indicated each time, indicating a hard error.

3. The method as claimed in claim 1, further comprising, upon indicating the hard error, fencing the first and second processors from a remaining portion of the multi-processor system.

4. The method as claimed in claim 3 wherein two other processors can be brought online once a hard error has been indicated and said original first and second processors have been fenced off.

5. The method as claimed in claim 1, wherein the first and second processors are provided on first and second individual chips, respectively, each of the first and second processors and each of the first and second chips being operable to perform cryptographic processing, wherein said first command includes an instruction to perform at least one of an encryption operation or a decryption operation.

6. The method as claimed in claim 1, further comprising isolating the hard error to a faulty one of the first and second processors by steps including:

submitting a second command to a third processor;

submitting the second command to the first processor;

executing the second command by the first processor and by the third processor;

comparing a result of executing the second command by the third processor with a result of executing the second command by the first processor;

submitting a third command to a third processor;

submitting the third command to the second processor;

executing the third command by the third processor and by the second processor;

comparing a result of executing the third command by the third processor with a result of executing the third command by the second processor; and

isolating one of the first and second processors as faulty when outcomes of comparing the results of executing the first, second and third commands by the one processor with the results of executing such commands by others of the first, second and third processors are that the results do not match.

7. The method of claim 6 further comprising taking the isolated faulty processor offline and brining online a different processor in place of said isolated faulty processor that has been taken offline.

8. The method as claimed in claim 6, wherein after isolating the faulty one of the first and second processors, removing the faulty one of the first and second processors from the active system configuration and utilizing the third processor in place of the faulty processor.

9. The method as claimed in claim 8, further comprising submitting a fourth command to a fourth processor;

submitting the fourth command to a processor selected from the group consisting of the first, second and third processors;

executing the fourth command by the fourth processor and by the selected processor;

comparing a result of executing the fourth command by the fourth processor with a result of executing the fourth command by the selected processor; and

when none of the results of executing the first, second, third and fourth commands by any of the first, second, third and fourth processors match any other results of executing the first, second, third and fourth commands by any of the first, second, third and fourth processors, isolating a fault to an element other than one of the first, second, third and fourth processors.

10. The method as claimed in claim 8, wherein the first, second and third processors are provided on first, second and third individual chips, respectively, each of the first, second and third processors and each of the first, second and third chips are operable to perform cryptographic processing, wherein the step of removing the faulty one of the first and second processors includes removing a faulty one of the individual chips from the active system configuration and the step of utilizing the third processor includes placing into the active system configuration the third chip in place of the faulty one of the individual chips.

11. The method as claimed in claim 8, wherein the first command is simultaneously executed by each of the first and second processors, the second command is simultaneously executed by each of the first and third processors and the third command is simultaneously executed by each of the second and third processors.

12. The method as claimed in claim 8, wherein the steps of comparing the results of executing the first, second and third commands by ones of the first, second and third processors includes generating a checksum for each of the results and determining whether the corresponding checksums match.

13. The method as claimed in claim 8, wherein the steps of comparing the results of executing the first, second and third commands by ones of the first, second and third processors includes generating a hash of each of the results and determining whether the corresponding hashes match.

14. A processing system, comprising:

at least a first processor and a second processor;

a controller operable to submit a command to the first and second processors for execution and to compare a result of executing the command by each of the first and second processors,

wherein the controller is operable to submit a first command to each of the first and second processors, each of the first and second processors is operable to execute the first command, and the controller is further operable to compare a first result of executing the first command by the first processor with a second result of executing the second command by the second processor and to indicate a hard error when the first result does not match the second result.

15. The processing system as claimed in claim 14, further comprising, wherein when said step of comparing indicates that the first result does not match the second result, the controller is further operable to submit the first command to the first and second processors for execution a predetermined number of times and to compare the first result to the second result produced each by the first and second processors each of the predetermined number of times, and to indicate the hard error when the first result does not match the second result each of the predetermined number of times.

16. The processing system as claimed in claim 15, wherein the controller is further operable upon indicating the hard error to fence the first arid second processors from a remaining portion of the multi-processor system.

17. The processing system as claimed in claim 15, wherein the first and second processors are provided on first and second individual chips, respectively, and each of the first and second processors and each of the first and second chips are operable to perform cryptographic processing.

18. The processing system as claimed in claim 15, further comprising:

a third processor, wherein the controller is further operable to submit a second command to the first processor and to the third processor for execution by the first and third processors, respectively, and to compare a result of executing the second command by the third processor with a result of executing the second command by the first processor, the controller being further operable to submit a third command to the second processor and to the third processor for execution by the second and third processors, respectively, and to compare a result of executing the third command by the third processor with a result of executing the third command by the second processor, such that the controller is operable to isolate one of the first and second processors as faulty when outcomes of comparing the result of executing the first, second and third commands by the one processor with the result of executing such commands by others of the first, second and third processors are that the results do not match.

19. The processing system as claimed in claim 18, wherein the controller is operable after isolating the faulty one of the first and second processors to remove the faulty one of the first and second processors from the active system configuration and to place the third processor into the active system configuration in place of the isolated faulty one of the first and second processors.

20. The processing system as claimed in claim 19, further comprising a fourth processor, wherein the controller is further operable to submit a fourth command for execution to the fourth processor and to a processor selected from the group consisting of the first, second and third processors and to compare a result of executing the fourth command by the fourth processor with a result of executing the fourth command by the selected processor, such that when none of the results of executing the first, second, third and fourth commands by any of the first, second, third and fourth processors match any other results of executing the first, second, third and fourth commands by any of the first, second, third and fourth processors, the controller is operable to isolate a fault to an element other than one of the first, second, third and fourth processors.

21. The processing system as claimed in claim 19, wherein the first, second and third processors are provided on first, second and third individual chips, respectively, each of the first, second and third processors and each of the first, second and third individual chips being operable to perform cryptographic processing, wherein the controller is operable to remove a faulty one of the individual chips from the active system configuration when the fault is isolated to a corresponding one of the first, second and third processors and the controller is operable to place into the active system configuration the third chip in place of the faulty one of the individual chips.

22. The processing system as claimed in claim 19, wherein the first and second processors are operable to execute the first command simultaneously, the first and third processors are operable to execute the second command simultaneously and the second and third processors are operable to execute the third command simultaneously.

23. The processing system as claimed in claim 19, wherein the ones of the first, second and third processors are operable to generate a checksum for each of the results of executing the corresponding ones of the first, second and third commands and to determine whether the corresponding checksums match.

24. The processing system as claimed in claim 19, wherein the ones of the first, second and third processors are operable to generate a hash of each of the results of executing the corresponding ones of the first, second and third commands and to determine whether the corresponding hashes match.