Multilayer interconnection substrate, semiconductor device, and solder resist

• US 20070221400A1
• Filed: 07/14/2006
• Published: 09/27/2007
• Est. Priority Date: 03/27/2006
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Mizutani, Daisuke, Kurashina, Mamoru
• Application Number:
  US11/486,061
• Publication Number:
  US 20070221400A1
• Time in Patent Office: Days
• US Class Current: 174/255
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/4922 having a heterogeneous or anisotropic structure
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 2201/029 Woven fibrous reinforcement or textile
• CPC Class Codes: H05K 3/281 by means of a preformed insulating foil H05K3/284 takes precedence
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602

Abstract

A multilayer interconnection substrate includes a resin laminated structure in which plural build-up layers are laminated, each of the plural build-up layers comprising an insulation layer and an interconnection pattern, and first and second solder resist layers provided on a top surface and a bottom surface of the resin laminated structure, wherein each of the first and second solder resist layers includes a glass cloth.

Claims

1. A multilayer interconnection substrate, comprising:

a resin laminated structure in which plural build-up layers are laminated, each of said plural build-up layers comprising an insulation layer and an interconnection pattern; and

first and second solder resist layers provided on a top surface and a bottom surface of said resin laminated structure,

wherein each of said first and second solder resist layers includes therein a glass cloth.

2. The multilayer interconnection substrate as claimed in claim 1, wherein each of said first and second solder resist layers has an elastic modulus larger than an elastic modulus of said resin laminated structure.

3. The multilayer interconnection structure as claimed in claim 1, wherein each of said first and second solder resist layers has an elastic modules of 10-30 GPa.

4. The multilayer interconnection structure as claimed in claim 1, wherein each of said first and second solder resist layers has a thickness of 30-60 μ

m.

5. The multilayer interconnection substrate as claimed in claim 1, wherein said multilayer interconnection substrate has a thickness from a surface of said first solder resist layer to a surface of said second solder resist layer of 500 μ

m or less.

6. The multilayer interconnection substrate as claimed in claim 1, wherein said first and second solder resist layers are formed with respective electrode pads.

7. The multilayer interconnection substrate as claimed in claim 1, wherein said glass cloth comprises a highly opened fabric cloth.

8. A semiconductor device, comprising:

a multilayer interconnection substrate; and

a semiconductor chip mounted upon said multilayer interconnection substrate in a face-down state,

said multilayer interconnection substrate comprising;

a resin laminated structure in which plural build-up layers are laminated, each of said plural build-up layers comprising an insulation layer and an interconnection pattern;

first and second solder resist layers provided on a top surface and a bottom surface of said resin laminated structure, each of said first and second solder resist layers including therein a glass cloth; and

an electrode pad formed to said of said first and second solder resist layers.

9. The semiconductor device as claimed in claim 8, wherein each of said first and second solder resist layers has an elastic modulus larger than an elastic modulus of said resin laminated structure.

10. The semiconductor device as claimed in claim 8, wherein each of said first and second solder resist layers has an elastic modulus of 10-30 GPa.

11. A solder resist, comprising:

a layer having a solder resist resin composition; and

a glass cloth impregnated in said layer of said solder resist resin composition.

12. The solder resist as claimed in claim 11, wherein said solder resist resin composition comprises any of an epoxy resin, an acrylic ester resin, and epoxy acrylate.