RFID SYSTEM COMPONENTS IMPLEMENTING ADJUSTED BACKSCATTER CALCULATIONS AND METHODS

• US 20070221737A2
• Filed: 04/25/2005
• Published: 09/27/2007
• Est. Priority Date: 01/21/2005
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Cooper, Scott, Diorio, Christopher, Humes, Todd, Sundstrom, Kurt
• Granted Patent: US 7,472,835 B2
• Time in Patent Office: Days
• US Class Current: 235/492
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: H03J 1/0058 provided with channel identification means arrangements for monitoring the use made of broadcast services H04H60/31

Abstract

RFID system components, such as readers and tags, communicate by a reader transmitting waveforms that encode a calibration symbol and a divide ratio. Tags include a processor to determine a backscatter link period result by dividing a count value representing the calibration symbol by the divide ratio and adding an adjustment. Tags modulate a backscatter waveform that includes symbols using a link period determined from the result.

Claims

1. An RFID tag comprising:

a demodulator to demodulate waveforms from an RFID reader that encode a gross number and a divide ratio;

a processor to determine a result by dividing the gross number by the divide ratio and adding an adjustment; and

a modulator to backscatter a tag waveform that includes symbols using a symbol period determined from the result.

2. The tag of claim 1, in which

it is further determined whether the adjustment is not needed, and

if so, the adjustment is not added.

3. The tag of claim 2, in which

the gross number is expressed in terms of bits, and

determining whether the adjustment is needed is determined from at least one but not all of the bits.

4. The tag of claim 1, in which

the gross number is expressed in terms of bits, and

dividing takes place by discarding at least one of the bits.

5. The tag of claim 1, in which

the adjustment is one of positive and negative.

6. The tag of claim 1, in which

the adjustment is added after dividing.

7. The tag of claim 1 in which the processor comprises:

a counter to count the gross number;

first and second multiplier circuits to multiply an output of the counter by first and second values, respectively, to provide first and second multiplied counts;

a multiplexing circuit to select either the first or second multiplied count based on the divide ratio;

an adder for adding the adjustment to an output of the multiplexing circuit; and

a divider circuit to divide an output of the adder.

8. The tag of claim 1 in which the processor comprises:

a counter to count the gross number, wherein the counter begins counting at a non-zero adjustment prior to counting the gross number; and

a divider to divide an output of the counter.

9. The tag of claim 1 in which the processor comprises:

a first counter to count the gross number, wherein the first counter begins counting at a first non-zero adjustment prior to counting the gross number;

a second counter to count the gross number, wherein the second counter begins counting at a second non-zero adjustment prior to counting the gross number;

first and second dividers to divide outputs of the first and second counters; and

a multiplexing circuit to select an output of either the first or second divider based upon a specified divide ratio.

10. The tag of claim 1, in which the processor is further adapted to

determine the gross number by counting a number of periodic events during a time duration of a feature of the reader waveform, and where the adjustment is added to the time duration.

11. The tag of claim 1, in which

the adjustment is added to the gross number before dividing.

12. The tag of claim 11, in which the processor is further adapted to

multiply by an integer before adding.

13. The tag of claim 1, in which

the adjustment is of fixed magnitude.

14. The tag of claim 1, in which the processor is further adapted to

determine a magnitude of the adjustment.

15. The tag of claim 14, in which

the magnitude is determined by looking up a value in a table.

16. The tag of claim 14, in which

the magnitude is determined from the divide ratio.

17. The tag of claim 14, in which

the gross number is expressed in terms of bits, and

the magnitude is determined from at least one but not all of the bits.

18. The tag of claim 1, in which the processor is further adapted to

determine the gross number by counting a number of periodic events during a time duration of a feature of the reader waveform, and

in which the number of periodic events is counted by a counter, and

the adjustment is added to the count.

19. The tag of claim 18, in which

the adjustment is one of positive and negative.

20. The tag of claim 18, in which

the adjustment is added one of before, concurrently with, and after counting.

21. A device comprising:

means for receiving waveforms from an RFID reader;

means for determining a gross number and a divide ratio from the waveforms;

means for generating a result by dividing the gross number by the divide ratio and adding an adjustment; and

means for backscattering a tag waveform that includes symbols using a symbol period determined from the result.

22. The device of claim 21, further comprising:

means for determining whether the adjustment is needed, and

if not, not adding the adjustment.

23. The device of claim 22, in which

the gross number is expressed in terms of bits, and

determining whether the adjustment is needed is determined from at least one but not all of the bits.

24. The device of claim 21, in which

the gross number is expressed in terms of bits, and

dividing takes place by discarding at least one of the bits.

25. The device of claim 21, in which

the adjustment is one of positive and negative.

26. The device of claim 21, in which

the adjustment is added after dividing.

27. The device of claim 21, in which

the adjustment is added to the gross number before dividing.

28. The device of claim 27, further comprising:

means for multiplying by an integer before adding.

29. The device of claim 21, in which

the adjustment is of fixed magnitude.

30. The device of claim 21, further comprising:

means for determining a magnitude of the adjustment.

31. The device of claim 30, in which

the magnitude is determined by looking up a value in a table.

32. The device of claim 30, in which

the magnitude is determined from the divide ratio.

33. The device of claim 30, in which

the gross number is expressed in terms of bits, and

the magnitude is determined from at least one but not all of the bits.

34. The device of claim 21, further comprising:

a counter for determining the gross number by counting a number of periodic events during a time duration of a feature of the reader waveform, and wherein the adjustment is added to the count.

35. The device of claim 34, in which

the adjustment is one of positive and negative.

36. The device of claim 34, in which

the adjustment is added one of before, concurrently with, and after counting.

37. The device of claim 21, in which determining the gross number comprises:

means for counting a number of periodic events during a time duration of a feature of the reader waveform, where the adjustment is added to the time duration.

38. A method for an RFID tag comprising:

receiving waveforms from an RFID reader;

determining a gross number and a divide ratio from the waveforms;

generating a result by dividing the gross number by the divide ratio and adding an adjustment; and

backscattering a tag waveform that includes symbols using a symbol period determined from the result.

39. The method of claim 38, further comprising:

determining whether the adjustment is needed, and

if not, not adding the adjustment.

40. The method of claim 39, in which

the gross number is expressed in terms of bits, and

determining whether the adjustment is needed is determined from at least one but not all of the bits.

41. The method of claim 38, in which

the gross number is expressed in terms of bits, and

dividing takes place by discarding at least one of the bits.

42. The method of claim 38, in which

the adjustment is one of positive and negative.

43. The method of claim 38, in which

the adjustment is added after dividing.

44. The method of claim 38, in which

the adjustment is added to the gross number before dividing.

45. The method of claim 44, further comprising:

multiplying by an integer before adding.

46. The method of claim 38, in which

the adjustment is of fixed magnitude.

47. The method of claim 38, further comprising:

determining a magnitude of the adjustment.

48. The method of claim 47, in which

the magnitude is determined by looking up a value in a table.

49. The method of claim 47, in which

the magnitude is determined from the divide ratio.

50. The method of claim 47, in which

the gross number is expressed in terms of bits, and

the magnitude is determined from at least one but not all of the bits.

51. The method of claim 38, further comprising:

determining the gross number by counting a number of periodic events during a time duration of a feature of the reader waveform,

the number of periodic events is counted in a counter, and

the adjustment is added to the count.

52. The method of claim 51, in which

the adjustment is one of positive and negative.

53. The method of claim 51, in which

the adjustment is added one of before, concurrently with, and after counting.

54. The method of claim 38, in which determining the gross number comprises:

counting a number of periodic events during a time duration of a feature of the reader waveform, where the adjustment is added to the time duration.

55. A circuit for an RFID tag having an antenna, comprising:

a demodulator to demodulate waveforms by the antenna that encode a gross number and a divide ratio;

a processor to determine a result by dividing the gross number by the divide ratio and adding an adjustment; and

a modulator to backscatter via the antenna a tag waveform that includes symbols using a symbol period determined from the result.

56. The circuit of claim 55, in which

it is further determined whether the adjustment is not needed, and

if so, the adjustment is not added.

57. The circuit of claim 56, in which

the gross number is expressed in terms of bits, and

determining whether the adjustment is needed is determined from at least one but not all of the bits.

58. The circuit of claim 55, in which

the gross number is expressed in terms of bits, and

dividing takes place by discarding at least one of the bits.

59. The circuit of claim 55, in which

the adjustment is one of positive and negative.

60. The circuit of claim 55, in which

the adjustment is added after dividing.

61. The circuit of claim 55 in which the processor comprises:

a counter to count the gross number;

first and second multiplier circuits to multiply an output of the counter by first and second values, respectively, to provide first and second multiplied counts;

a multiplexing circuit to select either the first or second multiplied count based on the divide ratio;

an adder for adding the adjustment to an output of the multiplexing circuit; and

a divider circuit to divide an output of the adder.

62. The circuit of claim 55 in which the processor comprises:

a counter to count the gross number, wherein the counter begins counting at a non-zero adjustment prior to counting the gross number; and

a divider to divide an output of the counter.

63. The circuit of claim 55 in which the processor comprises:

a first counter to count the gross number, wherein the first counter begins counting at a first non-zero adjustment prior to counting the gross number;

a second counter to count the gross number, wherein the second counter begins counting at a second non-zero adjustment prior to counting the gross number;

first and second dividers to divide outputs of the first and second counters; and

a multiplexing circuit to select an output of either the first or second divider based upon a specified divide ratio.

64. The circuit of claim 55, in which the processor is further adapted to

determine the gross number by counting a number of periodic events during a time duration of a feature of the reader waveform, and where the adjustment is added to the time duration.

65. The circuit of claim 55, in which

the adjustment is added to the gross number before dividing.

66. The circuit of claim 65, in which the processor is further adapted to multiply by an integer before adding.

67. The circuit of claim 55, in which

the adjustment is of fixed magnitude.

68. The circuit of claim 55, in which the processor is further adapted to

determine a magnitude of the adjustment.

69. The circuit of claim 68, in which

the magnitude is determined by looking up a value in a table.

70. The circuit of claim 68, in which

the magnitude is determined from the divide ratio.

71. The circuit of claim 68, in which

the gross number is expressed in terms of bits, and

the magnitude is determined from at least one but not all of the bits.

72. The circuit of claim 55, in which the processor is further adapted to

determine the gross number by counting a number of periodic events during a time duration of a feature of the reader waveform, and

in which the number of periodic events is counted by a counter, and

the adjustment is added to the count.

73. The circuit of claim 72, in which

the adjustment is one of positive and negative.

74. The circuit of claim 72, in which

the adjustment is added one of before, concurrently with, and after counting.

75. A circuit for an RFID tag having an antenna, comprising:

a demodulator to demodulate waveforms by the antenna that encode a gross number and a divide ratio;

a processor to determine a result by dividing the gross number by the divide ratio and adding an adjustment; and

a modulator to backscatter via the antenna a tag waveform that includes symbols using a symbol period determined from the result.

76. The circuit of claim 75, in which

it is further determined whether the adjustment is not needed, and

if so, the adjustment is not added.

77. The circuit of claim 76, in which

the gross number is expressed in terms of bits, and

determining whether the adjustment is needed is determined from at least one but not all of the bits.

78. The circuit of claim 75, in which

the gross number is expressed in terms of bits, and

dividing takes place by discarding at least one of the bits.

79. The circuit of claim 75, in which

the adjustment is one of positive and negative.

80. The circuit of claim 75, in which

the adjustment is added after dividing.

81. The circuit of claim 75 in which the processor comprises:

a counter to count the gross number;

first and second multiplier circuits to multiply an output of the counter by first and second values, respectively, to provide first and second multiplied counts;

a multiplexing circuit to select either the first or second multiplied count based on the divide ratio;

an adder for adding the adjustment to an output of the multiplexing circuit; and

a divider circuit to divide an output of the adder.

82. The circuit of claim 75 in which the processor comprises:

a counter to count the gross number, wherein the counter begins counting at a non-zero adjustment prior to counting the gross number; and

a divider to divide an output of the counter.

83. The circuit of claim 75 in which the processor comprises:

a first counter to count the gross number, wherein the first counter begins counting at a first non-zero adjustment prior to counting the gross number;

a second counter to count the gross number, wherein the second counter begins counting at a second non-zero adjustment prior to counting the gross number;

first and second dividers to divide outputs of the first and second counters; and

a multiplexing circuit to select an output of either the first or second divider based upon a specified divide ratio.

84. The circuit of claim 75, in which the processor is further adapted to

determine the gross number by counting a number of periodic events during a time duration of a feature of the reader waveform, and where the adjustment is added to the time duration.

85. The circuit of claim 75, in which

the adjustment is added to the gross number before dividing.

86. The circuit of claim 85, in which the processor is further adapted to multiply by an integer before adding.

87. The circuit of claim 75, in which

the adjustment is of fixed magnitude.

88. The circuit of claim 75, in which the processor is further adapted to

determine a magnitude of the adjustment.

89. The circuit of claim 88, in which

the magnitude is determined by looking up a value in a table.

90. The circuit of claim 88, in which

the magnitude is determined from the divide ratio.

91. The circuit of claim 88, in which

the gross number is expressed in terms of bits, and

the magnitude is determined from at least one but not all of the bits.

92. The circuit of claim 75, in which the processor is further adapted to

determine the gross number by counting a number of periodic events during a time duration of a feature of the reader waveform, and

in which the number of periodic events is counted by a counter, and

the adjustment is added to the count.

93. The circuit of claim 92, in which

the adjustment is one of positive and negative.

94. The circuit of claim 92, in which

the adjustment is added one of before, concurrently with, and after counting.