Nonvolatile semiconductor memory device

• US 20070221985A1
• Filed: 03/20/2007
• Published: 09/27/2007
• Est. Priority Date: 03/21/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Furuno, Makoto, Takano, Tamae, Yamazaki, Shunpei, Asami, Yoshinobu
• Granted Patent: US 7,692,232 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND

Abstract

A nonvolatile semiconductor memory device which is superior in writing and charge holding properties, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over an upper layer portion of the semiconductor substrate. It is preferable that a band gap of a semiconductor material forming the floating gate be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more. This is because, by decreasing the bottom energy level of a conduction band of the floating gate electrode to be lower than that of the channel formation region in the semiconductor substrate, carrier injecting and charge holding properties are improved.

Claims

1. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval; and

a first insulating layer, a floating gate, a second insulating layer, and a control gate which are provided at a position of an upper layer portion of the semiconductor substrate and about overlapped with the channel formation region,

wherein the floating gate is formed of a semiconductor material, and a band gap of the semiconductor material is smaller than a band gap of the channel formation region in the semiconductor substrate.

11. The nonvolatile semiconductor memory device according to claim 1, wherein there is a difference of 0.1 eV or more between the band gap of the channel formation region in the semiconductor substrate and the band gap of the semiconductor material forming the floating gate.

17. The nonvolatile semiconductor memory device according to claim 1, wherein the floating gate is in contact with the silicon nitride layer.

27. The nonvolatile semiconductor memory device according to claim 1,

wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate with plasma treatment, and

wherein the silicon nitride layer is formed by nitriding the silicon oxide layer with plasma treatment.

2. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval; and

a first insulating layer, a floating gate, a second insulating layer, and a control gate which are provided at a position of an upper layer portion of the semiconductor substrate and about overlapped with the channel formation region,

wherein the floating gate is formed of a material having a higher electron affinity than silicon.

18. The nonvolatile semiconductor memory device according to claim 2, wherein the floating gate is in contact with the silicon nitride layer.

28. The nonvolatile semiconductor memory device according to claim 2,

wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate with plasma treatment, and

wherein the silicon nitride layer is formed by nitriding the silicon oxide layer with plasma treatment.

3. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval; and

a first insulating layer, a floating gate, a second insulating layer, and a control gate which are provided at a position of an upper layer portion of the semiconductor substrate and about overlapped with the channel formation region,

wherein a barrier energy with respect to electrons of the floating gate, formed from the first insulating layer is higher than a barrier energy with respect to electrons of the channel formation region in the semiconductor substrate, formed from the first insulating layer.

19. The nonvolatile semiconductor memory device according to claim 3, wherein the floating gate is in contact with the silicon nitride layer.

29. The nonvolatile semiconductor memory device according to claim 3,

wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate with plasma treatment, and

wherein the silicon nitride layer is formed by nitriding the silicon oxide layer with plasma treatment.

4. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval; and

a first insulating layer, a floating gate, a second insulating layer, and a control gate which are provided at a position of an upper layer portion of the semiconductor substrate and about overlapped with the channel formation region,

wherein the floating gate is formed of germanium or a germanium compound.

13. The nonvolatile semiconductor memory device according to claim 4, wherein the germanium compound is germanium oxide or germanium nitride.

20. The nonvolatile semiconductor memory device according to claim 4, wherein the floating gate is in contact with the silicon nitride layer.

30. The nonvolatile semiconductor memory device according to claim 4,

wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate with plasma treatment, and

wherein the silicon nitride layer is formed by nitriding the silicon oxide layer with plasma treatment.

5. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval; and

a first insulating layer, a floating gate, a second insulating layer, and a control gate which are provided at a position of an upper layer portion of the semiconductor substrate and about overlapped with the channel formation region,

wherein the floating gate is formed of germanium or a germanium compound with a thickness of 1 nm or more and 20 nm or less.

14. The nonvolatile semiconductor memory device according to claim 5, wherein the germanium compound is germanium oxide or germanium nitride.

21. The nonvolatile semiconductor memory device according to claim 5, wherein the floating gate is in contact with the silicon nitride layer.

31. The nonvolatile semiconductor memory device according to claim 5,

wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate with plasma treatment, and

wherein the silicon nitride layer is formed by nitriding the silicon oxide layer with plasma treatment.

6. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval; and

a first insulating layer, a floating gate, a second insulating layer, and a control gate which are provided at a position of an upper layer portion of the semiconductor substrate and about overlapped with the channel formation region,

wherein the first insulating layer is formed of a stacked layer of silicon oxide layer and a silicon nitride layer on a semiconductor substrate side; and

wherein the floating gate is formed of a semiconductor material, and a band gap of the semiconductor material is smaller than a band gap of the channel formation region in the semiconductor substrate.

12. The nonvolatile semiconductor memory device according to claim 6, wherein there is a difference of 0.1 eV or more between the band gap of the channel formation region in the semiconductor substrate and the band gap of the semiconductor material forming the floating gate.

22. The nonvolatile semiconductor memory device according to claim 6, wherein the floating gate is in contact with the silicon nitride layer.

32. The nonvolatile semiconductor memory device according to claim 6,

wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate with plasma treatment, and

wherein the silicon nitride layer is formed by nitriding the silicon oxide layer with plasma treatment.

7. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval; and

a first insulating layer, a floating gate, a second insulating layer, and a control gate which are provided at a position of an upper layer portion of the semiconductor substrate and about overlapped with the channel formation region,

wherein the first insulating layer is formed of a stacked layer of silicon oxide layer and a silicon nitride layer on a semiconductor substrate side; and

wherein the floating gate is formed of a material having a higher electron affinity than silicon.

23. The nonvolatile semiconductor memory device according to claim 7, wherein the floating gate is in contact with the silicon nitride layer.

33. The nonvolatile semiconductor memory device according to claim 7,

wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate with plasma treatment, and

wherein the silicon nitride layer is formed by nitriding the silicon oxide layer with plasma treatment.

8. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval; and

a first insulating layer, a floating gate, a second insulating layer, and a control gate which are provided at a position of an upper layer portion of the semiconductor substrate and about overlapped with the channel formation region,

wherein the first insulating layer is formed of a stacked layer of silicon oxide layer and a silicon nitride layer on a semiconductor substrate side; and

wherein a barrier energy with respect to electrons of the floating gate, formed from the silicon oxide layer is higher than a barrier energy with respect to electrons of the channel formation region in the semiconductor substrate, formed from the silicon oxide layer.

24. The nonvolatile semiconductor memory device according to claim 8, wherein the floating gate is in contact with the silicon nitride layer.

34. The nonvolatile semiconductor memory device according to claim 8,

wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate with plasma treatment, and

wherein the silicon nitride layer is formed by nitriding the silicon oxide layer with plasma treatment.

9. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval; and

a first insulating layer, a floating gate, a second insulating layer, and a control gate which are provided at a position of an upper layer portion of the semiconductor substrate and about overlapped with the channel formation region,

wherein the first insulating layer is formed of a stacked layer of silicon oxide layer and a silicon nitride layer on a semiconductor substrate side; and

wherein the floating gate is formed of germanium or a germanium compound.

15. The nonvolatile semiconductor memory device according to claim 9, wherein the germanium compound is germanium oxide or germanium nitride.

25. The nonvolatile semiconductor memory device according to claim 9, wherein the floating gate is in contact with the silicon nitride layer.

35. The nonvolatile semiconductor memory device according to claim 9,

wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate with plasma treatment, and

wherein the silicon nitride layer is formed by nitriding the silicon oxide layer with plasma treatment.

10. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval; and

a first insulating layer, a floating gate, a second insulating layer, and a control gate which are provided at a position of an upper layer portion of the semiconductor substrate and about overlapped with the channel formation region,

wherein the first insulating layer is formed of a stacked layer of silicon oxide layer and a silicon nitride layer on a semiconductor substrate side; and

wherein the floating gate is formed of germanium or a germanium compound with a thickness of 1 nm or more and 20 nm or less.

16. The nonvolatile semiconductor memory device according to claim 10, wherein the germanium compound is germanium oxide or germanium nitride.

26. The nonvolatile semiconductor memory device according to claim 10, wherein the floating gate is in contact with the silicon nitride layer.

36. The nonvolatile semiconductor memory device according to claim 10,

wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate with plasma treatment, and

wherein the silicon nitride layer is formed by nitriding the silicon oxide layer with plasma treatment.