METHOD OF FORMING SILICIDED GATE STRUCTURE

• US 20070222000A1
• Filed: 05/31/2007
• Published: 09/27/2007
• Est. Priority Date: 05/13/2004
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tao, Hun-Jan, Shieh, Jyu-Horng, Chan, Bor-Wen
• Application Number:
  US11/756,131
• Publication Number:
  US 20070222000A1
• Time in Patent Office: Days
• US Class Current: 257/384
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain

Abstract

A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

Claims

1. An integrated circuit comprising a substrate having a plurality of gates formed thereon in a patterned region, at least some of said gates formed in an area of relative dense patterning in said patterned region and at least some of said gates formed in an area of relative non-dense patterning in said patterned region, and associated active regions formed therein, said active regions having a silicide formed therein and said gates having a silicide formed therein, wherein said gate silicide is thicker than said silicide formed in said active regions, wherein a gate height difference between said gates in said patterned region is less than 10%.

2. The integrated circuit of claim 1, wherein at least some of said gates are fully silicided.