Shielded through-via

• US 20070222021A1
• Filed: 03/10/2006
• Published: 09/27/2007
• Est. Priority Date: 03/10/2006
• Status: Active Grant

• Current Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Original Assignee: Rockwell Scientific Licensing LLC (Teledyne Technologies Incorporated)
• Inventors: Yao, Jun
• Granted Patent: US 7,589,390 B2
• Time in Patent Office: Days
• US Class Current: 257/499
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0222 for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
• CPC Class Codes: H05K 1/0239 Signal transmission by AC coupling
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2201/09645 Patterning on via walls; Plural lands around one hole
• CPC Class Codes: H05K 2201/09809 Coaxial layout
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A shielded through-via that reduces the effect of parasitic capacitance between the through-via and surrounding wafer while providing high isolation from neighboring signals. A shield electrode is formed in the insulating region and spaced apart from the through-via. A coupling element couples at least the time-varying portion of the signal carried on the through-via to the shield electrode. This reduces the effect of any parasitic capacitance between the through-via and the shield electrode, hence the surrounding wafer.

Claims

1. A shielded through-via, comprising:

a layer having first and second opposing surfaces and an insulating region there through,

a conductive through-via in the insulating region configured to carry a signal from the first surface to the opposing second surface,

a shield electrode in the insulating region spaced apart from the through-via, and

a coupling element that couples at least a time-varying portion of the signal carried on the through-via to the shield electrode.

2. The shielded through-via of claim 1, wherein the coupling element isolates the signal on the through-via from the signal coupled to the shield electrode.

3. The shielded through-via of claim 1, wherein the coupling element has approximately unity gain.

4. The shielded through-via of claim 1, wherein the coupling element has an output impedance less than ten ohms.

5. The shielded through-via of claim 1, wherein the coupling element has an input impedance comparable to or greater than the signal impedance.

6. The shielded through-via of claim 1, wherein the coupling element is selected from a buffer, an optical isolator or a MEMS isolator.

7. The shielded through-via of claim 1, wherein the coupling element couples at least the time-varying portion of the signal to the shield electrode on the second opposing surface.

8. The shielded through-via of claim 1, wherein said shield electrode is spaced apart from said layer.

9. The shielded through-via of claim 1, wherein the shield electrode circumscribes the through-via.

10. The shielded through-via of claim 1, wherein the length of the shield electrode is coextensive with the through-via.

11. The shielded through-via of claim 1, wherein the layer is a semi-conductive or conductive wafer.

12. The shielded through-via of claim 1, wherein the layer is one dielectric layer of a multi-layer metal interconnect stack.

13. The shielded through-via of claim 1, wherein the layer is a printed circuit board.

14. The shielded through-via of claim 1, wherein the layer is one layer of a multi-layer printed circuit board.

15. A shielded through-via, comprising:

a wafer of semi-conductive or conductive material having first and second opposing surfaces and an insulating region there through

a conductive through-via in the insulating region configured to carry a high impedance signal from the first surface along a signal path to the second opposing surface,

a shield electrode in the insulating region around the through-via and spaced apart from the through-via and the wafer, and

a unity gain isolator in the signal path that is configured to transform at least a time-varying portion of the high impedance signal from the through-via into a low impedance signal and apply the low impedance signal to the shield electrode and to a conductive line at the second opposing surface.

16. The shielded through-via of claim 15, wherein the unity gain isolator has an output impedance less than ten ohms.

17. The shielded through-via of claim 15, wherein the unity gain isolator has an input impedance comparable to or greater than the high impedance signal.

18. The shielded through-via of claim 15, wherein the unity gain isolator is selected from an electrical buffer, an optical isolator or a MEMS isolator.

19. A method of shielding a conductive through-via in an insulating region of a layer configured to carry a signal between first and second opposing surfaces of the layer, comprising:

forming a shield electrode in the insulating region spaced apart from the through-via, and

coupling at least a time-varying portion of the signal to the shield electrode.

20. The method of claim 19, wherein the signal is coupled to the shield electrode with approximately unity gain.

21. The method of claim 19, further comprising:

isolating the signal on the through-via from the signal coupled to the shield electrode.

22. The method of claim 19, wherein the signal on the through-via is a high-impedance signal, further comprising:

transforming the high-impedance signal into a low-impedance signal that is coupled the shield electrode.

23. A shielded through-via circuit, comprising:

a wafer having first and second opposing surfaces and an insulating region there through;

a signal generating device on said wafer, said device generating a time-varying signal indicative of changes in a device capacitance or a charge on the device capacitance;

a conductive through-via in the insulating region configured to carry the time-varying signal from the first surface to the second opposing surface;

a shield electrode in the insulating region spaced apart from the through-via; and

a unity gain isolator that is configured to couple the time-varying signal to the shield electrode and to a conductive line at the second opposing surface.

24. The shielded through-via circuit of claim 23, wherein the unity gain isolator has an output impedance less than ten ohms.

25. The shielded through-via circuit of claim 23, wherein the unity gain isolator has an input impedance comparable to or greater than the time-varying signal.

26. The shielded through-via circuit of claim 23, wherein the unity gain isolator is selected from an electrical buffer, an optical isolator or a MEMS isolator.