Amplifier

• US 20070222517A1
• Filed: 02/05/2007
• Published: 09/27/2007
• Est. Priority Date: 02/03/2006
• Status: Active Grant

• Current Assignee: National University of Singapore
• Original Assignee: National University of Singapore
• Inventors: Xu, Yong-Ping, Wu, Honglei
• Granted Patent: US 7,816,988 B2
• Time in Patent Office: Days
• US Class Current: 330/258
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/513 the amplifier being made for low supply voltages
• CPC Class Codes: H03F 2203/45418 the CMCL comprising a resistor addition circuit
• CPC Class Codes: H03F 2203/45454 the CSC comprising biasing means controlled by the input signal
• CPC Class Codes: H03F 3/45201 Non-folded cascode stages
• CPC Class Codes: H03F 3/45659 Controlling the loading circuit of the differential amplifier
• CPC Class Codes: H03F 3/45672 Controlling the common source circuit of the differential amplifier

Abstract

Briefly, one or more embodiments of an amplifier, including example applications, are described.

Claims

1. An apparatus comprising:

an amplifier;

said amplifier including at least an input stage and an output stage;

wherein, for said output stage, it is not necessary to trade off reduction in noise of an output signal with an increase in dynamic range of an output signal.

2. The apparatus of claim 1, wherein, for said output stage, noise performance does not substantially depend on transmittance of a particular transistor of said output stage.

3. The apparatus to claim 1, wherein, for said input stage, a trade off of reduction in noise of an output signal with an increase in dynamic range of an output signal is to be employed.

4. The apparatus of claim 1, wherein said amplifier is capable of providing a substantially rail-to-rail output voltage signal at a relatively low voltage.

5. The apparatus of claim 4, wherein said relatively low voltage comprises about one volt.

6. The apparatus of claim 2, wherein said amplifier output stage includes a DC rejection circuit.

7. The apparatus of claim 2, wherein said input stage includes a series-shunt feedback loop for controlling respective gate voltages of a pair of transistors of said input stage;

and

said output stage is coupled to said pair of transistors of the input stage such that respective gates of a pair of transistors of the output stage are coupled to the respective gates of said pair of transistors of the input stage.

8. An apparatus comprising:

an amplifier;

said amplifier including at least an input stage and an output stage;

wherein, for said output stage, noise performance depends at least in part on transmittance of the overall amplifier.

9. The apparatus of claim 8, wherein, for said output stage, noise performance does not substantially depend on transmittance of a particular transistor of said output stage.

10. The apparatus to claim 8, wherein, for said input stage, a trade off of reduction in noise of an output signal with an increase in dynamic range of an output signal is to be employed.

11. The apparatus of claim 8, wherein said amplifier is capable of providing a substantially rail-to-rail output voltage signal at a relatively low voltage.

12. The apparatus of claim 11, wherein said relatively low voltage comprises about one volt.

13. The apparatus of claim 9, wherein said amplifier output stage includes a DC rejection circuit.

14. The apparatus of claim 9, wherein said input stage includes a series-shunt feedback loop for controlling respective gate voltages of a pair of transistors of said input stage;

and

said output stage is coupled to said pair of transistors of the input stage such that respective gates of a pair of transistors of the output stage are coupled to the respective gates of said pair of transistors of the input stage.

15. An apparatus comprising:

means for amplifying a differential voltage signal;

said means for amplifying including at least an input stage and an output stage;

wherein, for said output stage, said means for amplifying includes a means for preventing a trade off between a reduction in noise of an output voltage signal and an increase in a dynamic range of the output voltage signal.

16. The apparatus to claim 15, wherein, for said input stage, said means for amplifying includes a means for trading off a reduction in noise of an output voltage signal with an increase in a dynamic range of the output voltage signal.

17. The apparatus of claim 15, wherein said means for amplifying includes means for providing a substantially rail-to-rail output voltage signal at a relatively low voltage.

18. The apparatus of claim 17, wherein said relatively low voltage comprises about one volt.

19. The apparatus of claim 16, wherein said output stage includes means for rejecting a DC voltage signal component.

20. A method of amplifying a differential voltage signal comprising:

applying the differential voltage signal to an input resistance;

employing a shunt-series feedback loop to produce a transconductance gain proportional to said input resistance; and

employing common mode feedback to remove a DC voltage signal component.

21. The method of claim 20, and further comprising:

producing an output voltage signal that is substantially rail-to-rail at a relatively low voltage.

22. The method of claim 21, wherein said relatively low voltage comprises about one volt.

23. An integrated circuit (IC) comprising:

an amplifier with DC rejection capability coupled to a successive approximation analog-to-digital converter (ADC);

wherein an output stage of said amplifier is capable of providing a substantially rail-to-rail output voltage signal without significantly increasing noise in the output voltage signal.

24. The IC of claim 23, wherein said ADC comprises an 11 bit ADC.

25. The integrated circuit of claim 23, wherein said IC is adapted to operate with a one volt power source.

26. The integrated circuit of claim 23, wherein said amplifier in employed in a configuration that includes a pseudo-resistor.

27. The integrated circuit of claim 23, wherein said amplifier and said ADC are coupled so as to provide a pseudo-sample and hold circuit.

28. The integrated circuit of claim 23, wherein said IC includes an oscillator to provide a clock signal;

wherein said oscillator is coupled to be turned on if said ADC is active and turned off otherwise.

29. An apparatus comprising:

means for amplifying a differential voltage signal, said means for amplifying including DC rejection;

said means for amplifying coupled to means for converting an analog signal to a digital signal by successive approximation;

wherein an output stage of said means for amplifying is capable of providing a substantially rail-to-rail output voltage signal without significantly increasing noise in the output voltage signal.

30. The apparatus of claim 29, wherein said means for converting comprises an 11 bit ADC.

31. The apparatus of claim 29, wherein said means for amplifying comprises means for operating with a one volt power source.

32. The apparatus of claim 29, wherein said means for amplifying including a pseudo-resistor.

33. The apparatus of claim 29, wherein said means for amplifying and said means for converting are coupled to provide a means for sampling and holding a signal value.

34. The apparatus of claim 29, and further including:

an oscillator to provide a clock signal;

wherein said oscillator is coupled to be turned on if said means for converting is active and turned off otherwise.

35. A method comprising:

amplifying a differential voltage signal including rejecting a DC component to provide an analog voltage signal;

converting the analog voltage signal to a digital signal by successive approximation; and

providing a substantially rail-to-rail output voltage signal from a one volt power source without significantly increasing noise in the output voltage signal.

36. The method of claim 35, and further comprising:

turning off an oscillator included to provide a clock signal if converting of the analog voltage signal is not taking place.

37. The method of claim 35, and further comprising:

sampling and holding the analog voltage signal so that said converting takes place.

38. A low noise operational transconductance amplifier (LN-OTA) comprising:

an input stage comprising a series-shunt feedback loop for controlling respective gate voltages of a first pair of transistors of the input stage; and

an output stage coupled to the first pair of transistors of the input stage such that respective gates of one pair of transistors of the output stage are coupled to the respective gates of said first pair of transistors of the input stage.

39. The LN-OTA of claim 38, wherein the input stage comprises a second pair of transistors, wherein gates of the second pair of transistors of the input stage are coupled to receive a differential voltage input, and wherein sources of the second pair of transistors of the input stage are coupled to respective drains of the first pair of transistors of the input stage.

40. The LN-OTA of claim 39, wherein the feedback loop comprises a resistor coupled between the sources of the second pair of transistors of the input stage.

41. The LN-OTA of claim 40, wherein the feedback loop further comprises a third pair of transistors in a cascade configuration with the second pair of transistors of the input stage.

42. A battery operated electronic device comprising:

a low noise operational transconductance amplifier (LN-OTA) comprising;

an input stage comprising a series-shunt feedback loop for controlling respective gate voltages of a first pair of transistors of the input stage; and

an output stage coupled to the first pair of transistors of the input stage such that respective gates of one pair of transistors of the output stage are coupled to the respective gates of said first pair of transistors of the input stage.

43. The device of claim 42, wherein said device is incorporated into an integrated circuit (IC) chip.