Dynamic Bias Control in Power Amplifier

• US 20070222519A1
• Filed: 03/08/2007
• Published: 09/27/2007
• Est. Priority Date: 03/22/2006
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Deng, Junxiong, Gudem, Prasad
• Granted Patent: US 7,729,672 B2
• Time in Patent Office: Days
• US Class Current: 330/285
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/0283 Reducing the number of DC-current paths
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier

Abstract

An RF output power amplifier (PA) of a cellular telephone includes first and second Class AB amplifier circuits. If the cellular telephone is to operate in a high power operating mode, then the first amplifier drives the PA output terminal. The power transistor(s) in the first amplifier is/are biased at a first DC current and a first DC voltage so as to optimize efficiency and linearity at high output powers. If the cellular telephone is to operate in a low power operating mode, then the second amplifier drives the output terminal. The power transistor(s) in the second amplifier is/are biased at a second DC current and a second DC voltage so as to optimize efficiency and linearity at low output powers. By sizing the power transistors in the amplifiers appropriately, emitter current densities are maintained substantially equal so that PA power gain is the same in the two operating modes.

Claims

1. A method comprising:

in a first operating mode, driving first signals onto an output terminal using a first Class AB amplifier circuit, wherein the first Class AB amplifier circuit includes a first power transistor that is biased at a first bias current I1 and at a first collector-to-emitter bias voltage V1, wherein the first signals are in a frequency band above one gigahertz, and wherein a second Class AB amplifier circuit is disabled during the first operating mode; and

in a second operating mode, driving second signals onto the output terminal using the second Class AB amplifier circuit, wherein the second Class AB amplifier circuit includes a second power transistor that is biased at a second bias current 12 and at a second collector-to-emitter bias voltage V2, wherein I1>

I2, wherein V1>

V2, wherein the first Class AB amplifier circuit is disabled during the second operating mode, wherein the second signals are in the frequency band above one gigahertz, and wherein the first and second Class AB amplifier circuits are integrated onto a single integrated circuit.

2. The method of claim 1, wherein the single integrated circuit is a WCDMA (Wideband Code Division Multiple Access) power amplifier integrated circuit.

3. The method of claim 1, wherein the first operating mode is a mode in which the first Class AB amplifier circuit delivers a higher average output power through the output terminal, wherein the second operating mode is a mode in which the second Class AB amplifier circuit delivers a lower average output power through the output terminal.

4. The method of claim 1, further comprising:

receiving a digital signal onto a terminal of the single integrated circuit, wherein if the digital signal has a first digital logic value then the first Class AB amplifier circuit drives the output terminal in the first operating mode, and wherein if the digital signal has a second digital logic value then the second Class AB amplifier circuit drives the output terminal in the second operating mode.

5. The method of claim 4, further comprising:

using a power detector to generate the digital signal.

6. The method of claim 4, further comprising:

generating the digital signal in a digital baseband integrated circuit.

7. The method of claim 1, wherein the second Class AB amplifier circuit further comprises a third power transistor, wherein in the second operating mode the second bias current I2 flows in a current path from a supply voltage node, through the second power transistor, through the third power transistor, and to a ground node.

8. The method of claim 1, wherein the first and second Class AB amplifier circuits are parts of a power amplifier, and wherein the power amplifier has a power gain that varies by less than five dB when an output power of the power amplifier varies over a forty dB range.

9. The method of claim 1, wherein the first power transistor in the first operating mode has a first DC bias current density, and wherein the second power transistor in the second operating mode has a second DC bias current density, wherein the first and second DC bias current densities are substantially identical.

10. The method of claim 1, wherein the first and second Class AB amplifier circuits are parts of a power amplifier, and wherein the power amplifier has an average power efficiency (APE) greater than four percent for a WCDMA (Wideband Code Division Multiple Access) output power PDF (Probability Distribution Function).

11. The method of claim 1, further comprising:

using an inductance to partially resonate an output capacitance of the first Class AB amplifier circuit, wherein an output node of the first Class AB amplifier circuit is coupled by a first conductor to a summing node, wherein the inductance is an inductance of a second conductor that extends from an output node of the second Class AB amplifier circuit and to the summing node.

12. The method of claim 1, wherein the first power transistor comprises a plurality of transistors that are connected in parallel, and wherein the second power transistor comprises a plurality of transistors that are connected in parallel.

13. The method of claim 1, wherein the first power transistor has an emitter and a collector, wherein the emitter is connected to a ground node, and wherein the collector is connected to the output terminal.

14. A circuit comprising:

an output terminal;

a first amplifier having an input lead and an output lead, the output lead being coupled to the output terminal, wherein the first amplifier includes a first power transistor that is biased at a first bias current I1 and at a first bias voltage V1;

a second amplifier having an input lead and an output lead, the output lead being coupled to the output terminal, wherein the second amplifier includes a second power transistor that is biased at a second bias current I2 and at a second bias voltage V2; and

an analog multiplexer having an input lead, a first output lead, a second output lead, and a select input lead, wherein if a first digital logic value is present on the select input lead then the analog multiplexer couples a signal on its input lead through the first output lead and onto the input lead of the first amplifier such that the first amplifier drives a power-amplified version of the signal onto the output terminal, wherein if a second digital logic value is present on the select input lead then the analog multiplexer couples the signal on its input lead through the second output lead and onto the input lead of the second amplifier such that the second amplifier drives a power-amplified version of the signal onto the output terminal, wherein the signal on the input lead of the multiplexer is in a frequency band above one gigahertz, wherein I1>

I2, wherein V1>

V2, wherein the first power transistor has a first DC bias current density when the first amplifier is driving the output terminal, wherein the second power transistor has a second DC bias current density when the second amplifier is driving the output terminal, wherein the first and second DC bias current densities are substantially identical.

15. The circuit of claim 14, wherein the circuit is an integrated circuit, the circuit further comprising:

an input terminal that is coupled to the select input lead of the analog multiplexer, wherein the input terminal and the output terminal are terminals of the integrated circuit.

16. The circuit of claim 14, further comprising:

a power detector that generates a digital signal, the digital signal being supplied onto the select input lead of the analog multiplexer.

17. The circuit of claim 14, wherein the circuit is a WCDMA (Wideband Code Division Multiple Access) power amplifier integrated circuit.

18. The circuit of claim 17, wherein the power amplifier has an average power efficiency (APE) greater than four percent for a WCDMA (Wideband Code Division Multiple Access) output power PDF (Probability Distribution Function).

19. The circuit of claim 14, wherein the second amplifier further includes a third power transistor, wherein the second bias current 12 flows in series through the second power transistor and then through the third power transistor.

20. The circuit of claim 14, wherein the circuit is a part of a driver amplifier in a transmitter chain, wherein the power-amplified version of the signal is output by the driver amplifier and is further amplified by a power amplifier.

21. A power amplifier capable of amplifying signals in a frequency band above one gigahertz with a power gain that varies by less than five dB when an output power of the power amplifier varies over a forty dB range, wherein the power amplifies has an ACPR (Adjacent Channel Power Ratio) of better than −

33 dBc for power amplifier output powers up to 26 dBm, and wherein the power amplifier has an average power efficiency (APE) greater than four percent for a WCDMA (Wideband Code Division Multiple Access) output power PDF (Probability Distribution Function).

22. The power amplifier of claim 21, wherein the power amplifier is part of an integrated circuit and comprises:

an output terminal from which the power amplifier outputs an amplified version of the signals in the frequency band;

a first amplifier circuit having an input and an output, wherein the output of the first amplifier circuit is coupled to the output terminal;

a second amplifier circuit having an input and an output, wherein the output of the second amplifier circuit is coupled to the output terminal; and

an analog multiplexer having a first output and a second output, wherein the first output is coupled to the input of the first amplifier circuit, and wherein the second output is coupled to the input of the second amplifier circuit.

23. The power amplifier of claim 22, wherein the integrated circuit further comprises:

a control terminal that is coupled to a select input of the analog multiplexer.