Method for locally suppressing a disturbance of a reference line

• US 20070223168A1
• Filed: 02/27/2007
• Published: 09/27/2007
• Est. Priority Date: 02/28/2006
• Status: Abandoned Application

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Vimercati, Daniele, Garofalo, Pierguido, Bolandrina, Efrem
• Application Number:
  US11/712,239
• Publication Number:
  US 20070223168A1
• Time in Patent Office: Days
• US Class Current: 361/118
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

Local suppression of a disturbance of a reference line is accomplished by supplying, on an internal node, a Band Gap voltage signal that is stable in temperature and power supply; driving a controlled current generator generating a controlled current signal by means of the Band Gap voltage signal; locally suppressing a disturbance of the reference line by means of a disturbance suppression circuit connected to the internal node acting on the Band Gap voltage signal; and mirroring a current signal generated on the reference line which is an output terminal of the Band Gap circuitry.

Claims

1. A method for locally suppressing a disturbance of a reference line comprising:

supplying, on an internal node, a Band Gap voltage signal that is stable in temperature and power supply;

driving a controlled current generator generating a controlled current signal by means of the Band Gap voltage signal;

locally suppressing a disturbance of the reference line by means of a disturbance suppression circuit connected to the internal node acting on the Band Gap voltage signal; and

mirroring a current signal generated on the reference line which is an output terminal of the Band Gap circuitry.

2. The method of claim 1, wherein locally suppressing the disturbance of the controlled current signal comprises emulating a behavior that is opposite to a behavior of a load circuit connected to the Band Gap circuitry.

3. The method of claim 1, wherein emulating provides for the use of a compensation capacitor connected to the Band Gap node and driven by an enable signal opposite to an enable signal of the Band Gap circuitry.

4. A method for generating a controlled current by means of a Band Gap circuitry comprising:

supplying, on a Band Gap node, a Band Gap voltage signal that is stable in temperature and power supply;

driving a controlled current generator by means of the Band Gap voltage signal;

locally suppressing a disturbance of a controlled current signal generated by the controlled current generator by means of a disturbance suppression circuit connected to the Band Gap node acting on the Band Gap voltage signal; and

mirroring the controlled current signal generated on an output terminal of the Band Gap circuitry.

5. The method of claim 4, wherein locally suppressing the disturbance of the controlled current signal comprises emulating a behavior that is opposite to a behavior of a load circuit connected to the Band Gap circuitry.

6. The method of claim 4, wherein emulating provides for the use of a compensation capacitor connected to the Band Gap node and driven by an enable signal opposite to an enable signal of the Band Gap circuitry.

7. A circuit for suppressing disturbances of a reference line where a controlled current signal is generated by a Band Gap circuitry on a Band Gap node comprising at least one compensation capacitor inserted between the Band Gap node and an inner circuit node of the disturbance suppression circuit, in turn connected to a first voltage reference by means of an input transistor having a control terminal connected to an input terminal of the disturbance suppression circuit and receiving an enable signal.

8. The circuit for suppressing disturbances of claim 7, further comprising at least one switch inserted between a second voltage reference and the inner circuit node.

9. The circuit for suppressing disturbances of claim 8, further comprising at least one threshold transistor inserted between the switch and the inner circuit node and having a control terminal connected to the Band Gap node.

10. The circuit for suppressing disturbances of claim 7, wherein the compensation capacitor comprises a transistor having a control terminal connected to the Band Gap node and conduction terminal connected to the inner circuit node.

11. The circuit for suppressing disturbances of claim 10, wherein the transistor is a MOS transistor with N channel.

12. The circuit for suppressing disturbances of claim 11, wherein the transistor has a bulk terminal connected to the first voltage reference.

13. The circuit for suppressing disturbances of claim 11, wherein the transistor is a Low Voltage transistor.

14. The circuit for suppressing disturbances of claim 7, wherein the input transistor has a first conduction terminal connected to the inner circuit node and a second conduction terminal connected to the first voltage reference.

15. The circuit for suppressing disturbances of claim 14, wherein the input transistor is a MOS transistor with N channel.

16. The circuit for suppressing disturbances of claim 15, wherein the input transistor has a bulk terminal connected to the first voltage reference.

17. The circuit for suppressing disturbances of claim 8, wherein the switch is a transistor having a control terminal connected to the input terminal, a first conduction terminal connected to the second voltage reference and a second conduction terminal connected to the inner circuit node.

18. The circuit for suppressing disturbances of claim 14, wherein the transistor is a MOS transistor with P channel.

19. The circuit for suppressing disturbances of claim 18, wherein the transistor has a bulk terminal connected to said second voltage reference.

20. The circuit for suppressing disturbances of claim 9, wherein the threshold transistor is a natural transistor in cascode configuration.

21. The circuit for suppressing disturbances of claim 20, wherein the threshold transistor has a bulk terminal connected to the first voltage reference.

22. The circuit for suppressing disturbances of claim 9, wherein the threshold transistor is a Low Voltage transistor.

29. The Band Gap circuitry of claim 20, wherein the transistor which realizes the coupling capacitor is a Low Voltage transistor having dimensions that may be compared with those of a transistor comprised in the controlled current generator.

23. A Band Gap circuitry, inserted between a first and a second voltage reference, comprising:

a controlled current generator, being connected to an input terminal receiving a Band Gap voltage signal that is stable in temperature and power supply;

a current mirror, being connected to an output terminal suitable for supplying a controlled current signal;

an enable circuitry, receiving an enable signal; and

a circuit for suppressing disturbances connected to the input terminal of the Band Gap circuitry.

24. The Band Gap circuitry of claim 23, wherein the circuit for suppressing disturbances comprises at least one compensation capacitor inserted between a Band Gap node and an inner circuit node, in turn connected to a first voltage reference by means of an input transistor having a control terminal connected to an input terminal of the disturbance suppression circuit and receiving an enable signal.

25. The Band Gap circuitry of claim 24, wherein the circuit for suppressing disturbances further comprises at least one switch inserted between a second voltage reference and the inner circuit node.

26. The Band Gap circuitry of claim 25, wherein the circuit for suppressing disturbances further comprises at least one threshold transistor inserted between the switch and the inner circuit node and having a control terminal connected to the Band Gap node.

27. The Band Gap circuitry of claim 26, wherein the compensation capacitor comprises a transistor having a control terminal connected to the Band Gap node and conduction terminal connected to the inner circuit node of the circuit for suppressing disturbances.

28. The Band Gap circuitry of claim 23, wherein the enable signal of the enable circuitry is the inverted signal of the enable signal of the disturbance suppression circuit.