Non-overlapping multi-stage clock generator system

• US 20070223633A1
• Filed: 03/22/2006
• Published: 09/27/2007
• Est. Priority Date: 03/22/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Kabir, Mohammad, Garrity, Douglas
• Granted Patent: US 7,649,957 B2
• Time in Patent Office: Days
• US Class Current: 375/354
• CPC Class Codes: H03K 5/1515 non-overlapping

Abstract

A multi-stage non-overlapping clock signal generator as described herein is suitable for use with a pipelined analog-to-digital converter architecture. The clock signal generator generally includes a back end clock generator, a second stage clock generator, and a first stage clock generator coupled in series. The clock signal generator may also include any number of intermediate stage clock generators coupled in series between the back end clock generator and the second stage clock generator. Example implementations of the various clock generator stages are also described herein.

Claims

1. A multi-stage clock generator architecture that generates multiple non-overlapping clock phases, the clock generator architecture comprising:

a back end clock generator having an input for a main clock signal, the back end clock generator being configured to generate, in response to the main clock signal, a first primary clock signal and a second primary clock signal that is non-overlapping with the first primary clock signal; and

a second stage clock generator coupled to the back end clock generator, the second stage clock generator having a first input for a first signal that is based upon the first primary clock signal and a second input for a second signal that is based upon the second primary clock signal, the second stage clock generator being configured to generate, in response to the first signal and the second signal, a first clock phase signal based upon the first primary clock signal, a second clock phase signal based upon the first primary clock signal, a third clock phase signal based upon the second primary clock signal, and a fourth clock phase signal based upon the second primary clock signal, the first, second, third, and fourth clock phase signals being mutually non-overlapping.

2. A multi-stage clock generator architecture according to claim 1, wherein:

the back end clock generator is configured to generate, in response to the main clock signal, a first delayed primary clock signal, a second delayed primary clock signal that is non-overlapping with the first delayed primary clock signal, a first complementary delayed primary clock signal, and a second complementary delayed primary clock signal that is non-overlapping with the first complementary delayed primary clock signal;

the second stage clock generator is configured to generate, in response to the first signal and the second signal, a first delayed clock phase signal based upon the first primary clock signal, a second delayed clock phase signal based upon the first primary clock signal, a third delayed clock phase signal based upon the second primary clock signal, a fourth delayed clock phase signal based upon the second primary clock signal, a first complementary delayed clock phase signal based upon the first primary clock signal, a second complementary delayed clock phase signal based upon the first primary clock signal, a third complementary delayed clock phase signal based upon the second primary clock signal, and a fourth complementary delayed clock phase signal based upon the second primary clock signal;

the first, second, third, and fourth delayed clock phase signals are mutually non-overlapping; and

the first, second, third, and fourth complementary delayed clock phase signals are mutually non-overlapping.

3. A multi-stage clock generator architecture according to claim 1, further comprising a first stage clock generator coupled to the second stage clock generator, the first stage clock generator being configured to generate, under the control of the second stage clock generator, a first first-stage clock signal and a second first-stage clock signal that is non-overlapping with the first first-stage clock signal.

4. A multi-stage clock generator architecture according to claim 3, the first stage clock generator comprising:

a first OR gate configured to receive the first and second clock phase signals, the first OR gate having an output node;

a second OR gate configured to receive the third and fourth clock phase signals, the second OR gate having an output node;

a first NOR gate having an input node coupled to the output node of the first OR gate, and having an output node for the second first-stage clock signal; and

a second NOR gate having an input node coupled to the output node of the second OR gate, and having an output node for the first first-stage clock signal.

5. A multi-stage clock generator architecture according to claim 3, the first stage clock generator comprising:

a first NOR gate having an input node configured to receive the main clock signal, and having an output node;

a synchronizing arrangement comprising an input node coupled to the output node of the first NOR gate, an enable input configured to receive an enable signal based upon the second primary clock signal, and an output node for the second first-stage clock signal; and

a second NOR gate having an input node configured to receive an inverted representation of the main clock signal, the second NOR gate being configured to generate an output upon which the first first-stage clock signal is based.

6. A multi-stage clock generator architecture according to claim 1, further comprising an intermediate clock generator stage having:

a first synchronization input node coupled to the back end clock generator to receive the first primary clock signal as a first synchronization signal;

a second synchronization input node coupled to the back end clock generator to receive the second primary clock signal as a second synchronization signal;

wherein

the intermediate clock generator is configured to generate, in response to the first synchronization signal and the second synchronization signal, a duplicate first primary clock signal corresponding to the first primary clock signal, and a duplicate second primary clock signal corresponding to the second primary clock signal; and

the duplicate second primary clock signal is non-overlapping with the duplicate first primary clock signal.

7. A multi-stage clock generator architecture according to claim 6, wherein:

the duplicate first primary clock signal corresponds to the first signal for the second stage clock generator; and

the duplicate second primary clock signal corresponds to the second signal for the second stage clock generator.

8. A multi-stage clock generator architecture according to claim 6, the intermediate clock generator comprising:

a first NOR gate having an input node configured to receive the main clock signal, and having an output node;

a first synchronizing arrangement comprising an input node coupled to the output node of the first NOR gate, an enable input configured to receive the second synchronization signal, and an output node for the duplicate second primary clock signal;

a second NOR gate having an input node configured to receive an inverted representation of the main clock signal, and having an output node; and

a second synchronizing arrangement comprising an input node coupled to the output node of the second NOR gate, an enable input configured to receive the first synchronization signal, and an output node for the duplicate first primary clock signal.

9. A clock generator that generates multiple non-overlapping clock phases, the clock generator comprising:

a first frequency divider having an input node for a first clock signal, and having an output node, the first frequency divider being configured to divide the first clock signal by two in frequency to obtain a first trigger signal at the output node of the first frequency divider;

a second frequency divider having an input node for a second clock signal, and having an output node, the second frequency divider being configured to divide the second clock signal by two in frequency to obtain a second trigger signal at the output node of the second frequency divider, the second clock signal being an inverted representation of the first clock signal;

a first clock signal generation branch coupled to the first and second frequency dividers, the first clock signal generation branch being configured to generate, in response to the first and second trigger signals, a first clock phase signal based upon the first clock signal;

a second clock signal generation branch coupled to the first and second frequency dividers, the second clock signal generation branch being configured to generate, in response to the first and second trigger signals, a second clock phase signal based upon the first clock signal;

a third clock signal generation branch coupled to the first and second frequency dividers, the third clock signal generation branch being configured to generate, in response to the first and second trigger signals, a third clock phase signal based upon the second clock signal; and

a fourth clock signal generation branch coupled to the first and second frequency dividers, the fourth clock signal generation branch being configured to generate, in response to the first and second trigger signals, a fourth clock phase signal based upon the second clock signal, the first, second, third, and fourth clock phase signals being mutually non-overlapping.

10. A clock generator according to claim 9, wherein:

the first clock signal generation branch is configured to generate, in response to the first and second trigger signals, a first delayed clock phase signal based upon the first clock phase signal, and a first complementary delayed clock phase signal based upon the first delayed clock phase signal;

the second clock signal generation branch is configured to generate, in response to the first and second trigger signals, a second delayed clock phase signal based upon the second clock phase signal, and a second complementary delayed clock phase signal based upon the second delayed clock phase signal;

the third clock signal generation branch is configured to generate, in response to the first and second trigger signals, a third delayed clock phase signal based upon the third clock phase signal, and a third complementary delayed clock phase signal based upon the third delayed clock phase signal;

the fourth clock signal generation branch is configured to generate, in response to the first and second trigger signals, a fourth delayed clock phase signal based upon the fourth clock phase signal, and a fourth complementary delayed clock phase signal based upon the fourth delayed clock phase signal;

the first, second, third, and fourth delayed clock phase signals are mutually non-overlapping; and

the first, second, third, and fourth complementary delayed clock phase signals are mutually non-overlapping.

11. A clock generator according to claim 9, further comprising:

a first non-overlap adjustment arrangement coupled between the first and third clock signal generation branches;

a second non-overlap adjustment arrangement coupled between the second and third clock signal generation branches;

a third non-overlap adjustment arrangement coupled between the second and fourth clock signal generation branches; and

a fourth non-overlap adjustment arrangement coupled between the first and fourth clock signal generation branches.

12. A clock generator according to claim 9, further comprising:

an input node for a main clock signal, the first and second clock signals being derived from the main clock signal;

a first synchronization input node for a first synchronization signal derived from the main clock signal;

a second synchronization input node for a second synchronization signal derived from the main clock signal, wherein the second synchronization signal is non-overlapping with the first synchronization signal;

a first synchronizing arrangement within the first clock signal generation branch, the first synchronizing arrangement comprising an enable input configured to receive the first synchronization signal, and an output node for the first clock phase signal;

a second synchronizing arrangement within the second clock signal generation branch, the second synchronization arrangement comprising an enable input configured to receive the first synchronization signal, and an output node for the second clock phase signal;

a third synchronizing arrangement within the third clock signal generation branch, the third synchronizing arrangement comprising an enable input configured to receive the second synchronization signal, and an output node for the third clock phase signal; and

a fourth synchronizing arrangement within the fourth clock signal generation branch, the fourth synchronizing arrangement comprising an enable input configured to receive the second synchronization signal, and an output node for the fourth clock phase signal.

13. A multi-stage clock generator architecture that generates multiple non-overlapping clock phases, the clock generator architecture comprising:

a back end clock generator having an input for a main clock signal, the back end clock generator being configured to generate, in response to the main clock signal, a first primary clock signal and a second primary clock signal that is non-overlapping with the first primary clock signal; and

a second stage clock generator coupled to the back end clock generator, and operable in response to the first and second primary clock signals, the second stage clock generator comprising;

a first frequency divider having an input node for a first clock signal derived from the main clock signal, and having an output node, the first frequency divider being configured to divide the first clock signal by two in frequency to obtain a first trigger signal at the output node of the first frequency divider;

a second frequency divider having an input node for a second clock signal derived from the main clock signal, and having an output node, the second frequency divider being configured to divide the second clock signal by two in frequency to obtain a second trigger signal at the output node of the second frequency divider, the second clock signal being an inverted representation of the first clock signal; and

a plurality of clock signal generation branches coupled to the first and second frequency dividers, each of the plurality of clock signal generation branches being configured to generate, in response to the first and second trigger signals, a different non-overlapping clock phase signal based upon the first clock signal or the second clock signal.

14. A multi-stage clock generator architecture according to claim 13, wherein:

each of the plurality of clock signal generation branches is configured to generate, in response to the first and second trigger signals, a respective delayed clock phase signal and a respective complementary delayed clock phase signal;

all of the delayed clock phase signals are mutually non-overlapping; and

all of the complementary delayed clock phase signals are mutually non-overlapping.

15. A multi-stage clock generator architecture according to claim 13, the second stage clock generator further comprising:

an input node for the main clock signal;

a first synchronization input node for a first synchronization signal derived from the first primary clock signal; and

a second synchronization input node for a second synchronization signal derived from the second primary clock signal, wherein the second synchronization signal is non-overlapping with the first synchronization signal;

wherein

each of the plurality of clock signal generation branches includes a respective synchronizing arrangement comprising an enable input configured to receive the first or second synchronization signal, and an output node for its respective non-overlapping clock phase signal.

16. A multi-stage clock generator architecture according to claim 13, wherein the back end clock generator is configured to generate, in response to the main clock signal, a first delayed primary clock signal, a second delayed primary clock signal that is non-overlapping with the first delayed primary clock signal, a first complementary delayed primary clock signal, and a second complementary delayed primary clock signal that is non-overlapping with the first complementary delayed primary clock signal.

17. A multi-stage clock generator architecture according to claim 13, further comprising a first stage clock generator coupled to the second stage clock generator, the first stage clock generator being configured to generate, under the control of the second stage clock generator, a first first-stage clock signal and a second first-stage clock signal that is non-overlapping with the first first-stage clock signal.

18. A multi-stage clock generator architecture according to claim 13, further comprising an intermediate clock generator stage having:

a first synchronization input node coupled to the back end clock generator to receive the first primary clock signal as a first synchronization signal;

a second synchronization input node coupled to the back end clock generator to receive the second primary clock signal as a second synchronization signal;

wherein

the intermediate clock generator is configured to generate, in response to the first synchronization signal and the second synchronization signal, a duplicate first primary clock signal corresponding to the first primary clock signal, and a duplicate second primary clock signal corresponding to the second primary clock signal; and

the duplicate second primary clock signal is non-overlapping with the duplicate first primary clock signal.

19. A multi-stage clock generator architecture according to claim 18, wherein:

the duplicate first primary clock signal corresponds to a duplicate first synchronization signal for the second stage clock generator; and

the duplicate second primary clock signal corresponds to a duplicate second synchronization signal for the second stage clock generator.