Non-overlapping multi-stage clock generator system
First Claim
1. A multi-stage clock generator architecture that generates multiple non-overlapping clock phases, the clock generator architecture comprising:
- a back end clock generator having an input for a main clock signal, the back end clock generator being configured to generate, in response to the main clock signal, a first primary clock signal and a second primary clock signal that is non-overlapping with the first primary clock signal; and
a second stage clock generator coupled to the back end clock generator, the second stage clock generator having a first input for a first signal that is based upon the first primary clock signal and a second input for a second signal that is based upon the second primary clock signal, the second stage clock generator being configured to generate, in response to the first signal and the second signal, a first clock phase signal based upon the first primary clock signal, a second clock phase signal based upon the first primary clock signal, a third clock phase signal based upon the second primary clock signal, and a fourth clock phase signal based upon the second primary clock signal, the first, second, third, and fourth clock phase signals being mutually non-overlapping.
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Abstract
A multi-stage non-overlapping clock signal generator as described herein is suitable for use with a pipelined analog-to-digital converter architecture. The clock signal generator generally includes a back end clock generator, a second stage clock generator, and a first stage clock generator coupled in series. The clock signal generator may also include any number of intermediate stage clock generators coupled in series between the back end clock generator and the second stage clock generator. Example implementations of the various clock generator stages are also described herein.
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Citations
19 Claims
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1. A multi-stage clock generator architecture that generates multiple non-overlapping clock phases, the clock generator architecture comprising:
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a back end clock generator having an input for a main clock signal, the back end clock generator being configured to generate, in response to the main clock signal, a first primary clock signal and a second primary clock signal that is non-overlapping with the first primary clock signal; and
a second stage clock generator coupled to the back end clock generator, the second stage clock generator having a first input for a first signal that is based upon the first primary clock signal and a second input for a second signal that is based upon the second primary clock signal, the second stage clock generator being configured to generate, in response to the first signal and the second signal, a first clock phase signal based upon the first primary clock signal, a second clock phase signal based upon the first primary clock signal, a third clock phase signal based upon the second primary clock signal, and a fourth clock phase signal based upon the second primary clock signal, the first, second, third, and fourth clock phase signals being mutually non-overlapping. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A clock generator that generates multiple non-overlapping clock phases, the clock generator comprising:
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a first frequency divider having an input node for a first clock signal, and having an output node, the first frequency divider being configured to divide the first clock signal by two in frequency to obtain a first trigger signal at the output node of the first frequency divider;
a second frequency divider having an input node for a second clock signal, and having an output node, the second frequency divider being configured to divide the second clock signal by two in frequency to obtain a second trigger signal at the output node of the second frequency divider, the second clock signal being an inverted representation of the first clock signal;
a first clock signal generation branch coupled to the first and second frequency dividers, the first clock signal generation branch being configured to generate, in response to the first and second trigger signals, a first clock phase signal based upon the first clock signal;
a second clock signal generation branch coupled to the first and second frequency dividers, the second clock signal generation branch being configured to generate, in response to the first and second trigger signals, a second clock phase signal based upon the first clock signal;
a third clock signal generation branch coupled to the first and second frequency dividers, the third clock signal generation branch being configured to generate, in response to the first and second trigger signals, a third clock phase signal based upon the second clock signal; and
a fourth clock signal generation branch coupled to the first and second frequency dividers, the fourth clock signal generation branch being configured to generate, in response to the first and second trigger signals, a fourth clock phase signal based upon the second clock signal, the first, second, third, and fourth clock phase signals being mutually non-overlapping. - View Dependent Claims (10, 11, 12)
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13. A multi-stage clock generator architecture that generates multiple non-overlapping clock phases, the clock generator architecture comprising:
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a back end clock generator having an input for a main clock signal, the back end clock generator being configured to generate, in response to the main clock signal, a first primary clock signal and a second primary clock signal that is non-overlapping with the first primary clock signal; and
a second stage clock generator coupled to the back end clock generator, and operable in response to the first and second primary clock signals, the second stage clock generator comprising;
a first frequency divider having an input node for a first clock signal derived from the main clock signal, and having an output node, the first frequency divider being configured to divide the first clock signal by two in frequency to obtain a first trigger signal at the output node of the first frequency divider;
a second frequency divider having an input node for a second clock signal derived from the main clock signal, and having an output node, the second frequency divider being configured to divide the second clock signal by two in frequency to obtain a second trigger signal at the output node of the second frequency divider, the second clock signal being an inverted representation of the first clock signal; and
a plurality of clock signal generation branches coupled to the first and second frequency dividers, each of the plurality of clock signal generation branches being configured to generate, in response to the first and second trigger signals, a different non-overlapping clock phase signal based upon the first clock signal or the second clock signal. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification