Method for wafer level package of sensor chip

• US 20070224728A1
• Filed: 03/22/2006
• Published: 09/27/2007
• Est. Priority Date: 03/22/2006
• Status: Active Grant

• Current Assignee: National Taiwan University (Government of The Republic of China)
• Original Assignee: National Taiwan University (Government of The Republic of China)
• Inventors: Yang, Rou-Ching, Wu, Enboa
• Granted Patent: US 7,351,609 B2
• Time in Patent Office: Days
• US Class Current: 438/106
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for wafer level package (WLP) of sensor chips is provided, including the steps of: providing a wafer, the wafer including a plurality of die regions, each the die region on a first surface of the wafer comprising an active area and a pad surrounding the active area; bounding a transparent protective layer to the first surface of the wafer; forming a stress buffer on a second surface of the wafer; using etching or laser drill to form a via hole at the location between two neighboring die regions through the stress buffer and the wafer to expose the pad or a conductive line between two neighboring pads; and forming a plurality of bump electrodes on the stress buffer for electrical connection to the pads through the via holes. The method can prevent pollution of the die, improve the convenience of package, reduce the manufacture cost, increase the package reliability, and solve the stress problem caused by attaching the die directly to the PCB.

Claims

1. A method for wafer level package (WLP) of sensor chips, comprising the steps of:

(a) providing a wafer, the wafer including a plurality of die regions, each die region on a first surface of the wafer comprising an active area and a pad surrounding the active area;

(b) bounding a transparent protective layer to the first surface of the wafer;

(c) forming a stress buffer on a second surface of the wafer;

(d) using an etching technique to form a via hole at the location between two neighboring die regions through the stress buffer and the wafer to expose the pad or a conductive line between two neighboring pads; and

(e) forming a plurality of bump electrodes on the stress buffer for electrical connection to the pads through the via holes.

2. The method as claimed in claim 1, wherein the etching technique is a wet etching technique.

3. The method as claimed in claim 2, where in the wet etching technique is a chemical etching technique.

4. The method as claimed in claim 1, wherein the etching technique is a dry etching technique.

5. The method as claimed in claim 4, wherein the dry etching technique is a reactive ion etching technique.

6. The method as claimed in claim 4, wherein the dry etching technique is an inductively coupled plasma reactive ion etching technique.

7. The method as claimed in claim 1, wherein the transparent protective layer is made of glass, crystal, sapphire, or a combination of the above.

8. The method as claimed in claim 1, wherein at least one surface of the transparent protective layer comprises a coated film.

9. The method as claimed in claim 1, wherein at least one surface of the transparent protective layer comprises a dichroic.

10. The method as claimed in claim 1, wherein at least one surface of the transparent protective layer comprises a light grid (grating).

11. The method as claimed in claim 1, wherein at least one surface of the transparent protective layer comprises a light wave filter layer.

12. The method as claimed as in claim 1, wherein the stress buffer layer is made of material selected from a group formed by PI, BCB, and silicon.

13. The method as claimed in claim 1, wherein the inside of the via hole further comprises a conductive material.

14. The method as claimed in claim 13, wherein the conductive material is selected from a group formed by Ti, Cu, Cr, Au, Al, Ni, V, and Ag.

15. The method as claimed in claim 13, wherein the conductive material is formed inside of the via hole with a sputtering technique.

16. The method as claimed in claim 13, wherein the conductive material is formed inside of the via hole with an electroplating technique.

17. The method as claimed in claim 13, wherein the conductive material is formed inside of the via hole with an evaporation technique.

18. The method as claimed in claim 13, wherein the conductive material is formed inside of the via hole with an electroless plating technique.

19. A method for wafer level package (WLP) of sensor chips, comprising the steps of:

(i) providing a wafer, the wafer including a plurality of die regions, each die region on a first surface of the wafer comprising an active area and a pad surrounding the active area;

(ii) placing a conductive line between the pads of two neighboring die regions;

(iii) bounding a transparent protective layer to the first surface of the wafer;

(iv) forming a stress buffer on a second surface of the wafer;

(v) using an etching technique to form a via hole at the location between two neighboring die regions through the stress buffer and the wafer to expose the conductive line; and

(vi) forming a plurality of bump electrodes on the stress buffer for electrical connection to the pads through the via holes and the conductive line.

20. The method as claimed in claim 19, wherein the etching technique is a wet etching technique.

21. The method as claimed in claim 20, where in the wet etching technique is a chemical etching technique.

22. The method as claimed in claim 19, wherein the etching technique is a dry etching technique.

23. The method as claimed in claim 22, wherein the dry etching technique is a reactive ion etching technique.

24. The method as claimed in claim 22 wherein the dry etching technique is an inductively coupled plasma reactive ion etching technique.

25. The method as claimed in claim 19, wherein the transparent protective layer is made of glass, crystal, sapphire, or a combination of the above.

26. The method as claimed in claim 19, wherein at least one surface of the transparent protective layer comprises a coated film.

27. The method as claimed in claim 19, wherein at least one surface of the transparent protective layer comprises a dichroic.

28. The method as claimed in claim 19, wherein at least one surface of the transparent protective layer comprises a light grid (grating).

29. The method as claimed in claim 19, wherein at least one surface of the transparent protective layer comprises a wave filter layer.

30. The method as claimed as in claim 19, wherein the stress buffer layer is made of material selected from a group formed by PI, BCB, and silicon.

31. The method as claimed in claim 19, wherein the inside of the via hole further comprises a conductive material.

32. The method as claimed in claim 31, wherein the conductive material is selected from a group formed by Ti, Cu, Cr, Au, Al, Ni, V, and Ag.

33. The method as claimed in claim 31, wherein the conductive material is formed inside of the via hole with a sputtering technique.

34. The method as claimed in claim 31, wherein the conductive material is formed inside of the via hole with an electroplating technique.

35. The method as claimed in claim 31, wherein the conductive material is formed inside of the via hole with an evaporation technique.

36. The method as claimed in claim 31, wherein the conductive material is formed inside of the via hole with an electroless plating technique.

37. A method for wafer level package (WLP) of sensor chips, comprising the steps of:

(1) providing a wafer, the wafer including a plurality of die regions, each die region on a first surface of the wafer comprising an active area and a pad surrounding the active area;

(2) bounding a transparent protective layer to the first surface of the wafer;

(3) forming a stress buffer on a second surface of the wafer;

(4) using laser drill to form a via hole at the location between two neighboring die regions through the stress buffer and the wafer to expose the pad or a conductive line between two neighboring pads; and

(5) forming a plurality of bump electrodes on the stress buffer for electrical connection to the pads through the via holes.

38. The method as claimed in claim 37, further comprising a step of placing a conductive line between the pads of two neighboring die regions between the step (1) and the step (2).