PATCHABLE AND/OR PROGRAMMABLE DECODE USING PREDECODE SELECTION

• US 20070226463A1
• Filed: 03/28/2006
• Published: 09/27/2007
• Est. Priority Date: 03/03/2006
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Jacobson, Quinn, Caprioli, Paul, Chaudhry, Shailender, Tremblay, Marc
• Granted Patent: US 7,353,363 B2
• Time in Patent Office: Days
• US Class Current: 712/209
• CPC Class Codes: G06F 9/30196 using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
• CPC Class Codes: G06F 9/328 for runtime instruction patching
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a configurable predecode mechanism can be employed to select, for respective instruction patterns, between fixed decode and programmable decode paths provided by a processor. In this way, a patchable and/or programmable decode mechanism can be efficiently provided. In some realizations, either (or both) predecode or (and) decode may be configured or reconfigured post-manufacture. In some realizations, either (or both) predecode or (and) decode may be configured at (or about) initialization. In some realizations, either (or both) predecode or (and) decode may be configured at run-time.

Claims

1. A processor that implements an instruction set, wherein at least some of the instructions thereof are natively executed and at least some instructions thereof are expanded for execution as counterpart sequences of one or more operations, and wherein the set of instructions expanded for execution is modifiable post manufacture using a programmable predecode block of the processor.

2. The processor of claim 1,

wherein the counterpart sequences of operations are themselves modifiable post manufacture.

3. A processor comprising:

an instruction decode block including both a fixed decode path and a configurable decode path that includes a programmable multi-entry store from which, for a first subset, less that all, of instructions executed by the processor, programmable sequences of one or more decoded operations are generated; and

a predecode path that is configurable to select, for respective instruction patterns, one of the fixed decode path and the configurable decode path.

4. The processor of claim 3,

wherein both the configurable predecode path and the configurable decode path are reconfigurable post-manufacture of the processor.

5. The processor of claim 4,

wherein either or both the configurable predecode path and the configurable decode path are reconfigurable coincident with initialization of the processor.

6. The processor of claim 4,

wherein either or both the configurable predecode path and the configurable decode path are reconfigurable at run-time.

7. The processor of claim 3,

wherein the programmable store of the configurable decode path is indexed using predecode information supplied from the configurable predecode path.

8. The processor of claim 3,

wherein the configurable predecode path includes a programmable multi-entry store, wherein individual entries thereof correspond to respective instruction patterns and are programmable to encode, for at least some of the instruction patterns, respective identifiers into the programmable store of the configurable decode path.

9. The processor of claim 3,

wherein the configurable predecode path includes a programmable multi-entry store, wherein individual entries thereof include codings selective, for at least some programmings and instruction patterns, for one of the fixed decode path and the configurable decode path.

10. The processor of claim 3, further comprising:

an instruction store coupled between the configurable predecode path and the instruction decode block, the instruction store including storage for predecode information in association with instructions,

wherein at least some of the predecode information is selective for one of the fixed instruction decode path and the configurable instruction decode path.

11. The processor of claim 10, further comprising:

replicated fetch-decode paths,

wherein the instruction store includes a fetch buffer of at least one of the fetch-decode paths.

12. The processor of claim 10, embodied as a computing system and further comprising:

a memory hierarchy coupled to supply the instruction store with instructions for predecode and decode.

13. The processor of claim 3, embodied as one of:

a processor integrated circuit; and

media encoding a design file representation of the processor.

14. A method of operating a processor, the method comprising:

for a given instruction sequence including at least two instruction patterns, decoding at least a first one of instruction patterns using a fixed decode path and decoding at least a second one of instruction patterns using a configurable decode path; and

selecting, for a given instruction pattern, either the fixed decode path or the configurable decode path,

wherein the selecting is performed at predecode using a configurable predecode facility.

15. The method of claim 14,

encoding the selection as predecode information.

16. The method of claim 14,

wherein the configurable decode path includes a programmable store;

and

wherein at least for instructions corresponding to the second instruction pattern, the configurable predecode facility is selective for one or more corresponding entries of the programmable store.

17. The method of claim 14,

executing as part of a single thread of execution, both instructions decoded using the fixed decode path and instructions decoded using the configurable decode path.

18. The method of claim 14, further comprising:

configuring either or both of the configurable predecode facility and the configurable decode path post manufacture, coincident with initialization of the processor, or at run-time.

19. A computer program product comprising:

a computer readable encoding of an instruction sequence of instructions executable by a processor, the instruction sequence consisting of instructions from an instruction set implemented by the processor;

the instruction sequence executable by the processor to define content of a programmable decode store of the processor, thereby defining decode information of the processor for at least a subset of instructions of the instruction set and modifying execution behavior of the processor.

20. A computer program product as recited in claim 19,

wherein execution of the instruction sequence results in patching a configurable predecode facility of the process to select, for the subset of instructions, decode information defined in the programmable decode store.

21. A computer program product as recited in claim 19,

wherein execution of the instruction sequence results in redefinition of decode information for an instruction set instruction natively supported by the processor.

22. A computer program product as recited in claim 19,

wherein execution of the instruction sequence results in an extension to the instruction set.

23. An apparatus comprising:

means for decoding at least a first instruction pattern of an instruction sequence using a fixed decode path;

means for decoding at least a second instruction pattern of the instruction sequence using a configurable decode path; and

means for selecting, for a given instruction pattern, either the fixed decode path or the configurable decode path, wherein the selecting means includes configurable predecode means.