EFFECTIVE ELIMINATION OF DELAY SLOT HANDLING FROM A FRONT SECTION OF A PROCESSOR PIPELINE

• US 20070226475A1
• Filed: 09/21/2006
• Published: 09/27/2007
• Est. Priority Date: 03/13/2006
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Jacobson, Quinn A., Chaudhry, Shailender, Tremblay, Marc
• Granted Patent: US 7,634,644 B2
• Time in Patent Office: Days
• US Class Current: 712/234
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

Architectural techniques and implementations that defer enforcement of certain delayed control transfer instruction (DCTI) sequencing constraints or conventions to later stages of an execution pipeline are described. In this way, complexity of a processor pipeline front-end (including fetch sequencing) can be simplified, at least in-part, by fetching instructions generally without regard to such constraints or conventions. Instead, enforcement of such sequencing constraints and/or conventions may be deferred to one or more pipeline stages associated with commitment or retirement of instructions. Higher fetch bandwidth may be achieved in some realizations when, for example, DCTI couples are encountered in an execution sequence.

Claims

1. A computing apparatus configured to execute an instruction set that includes at least one delayed control transfer type instruction (DCTI), the computing apparatus comprising:

a pipeline front-end for fetching instructions from an instruction store generally without regard to an architecturally-defined special branching behavior for program sequences that include a second DCTI in the delay slot of a first DCTI; and

a downstream pipeline section configured to identify in a speculatively executed instruction sequence, a subsequence containing the second DCTI in the delay slot of the first DCTI and to enforce the architecturally-defined special branching behavior.

2. The computing apparatus of claim 1,

wherein the downstream pipeline section includes a commit stage for committing executed instructions to architectural state, the commit stage enforcing the architecturally-defined special branching behavior.

3. The computing apparatus of claim 1,

wherein the pipeline front-end lacks capability to determine proper execution order for nested DCTIs within fetched groups of instructions.

4. The computing apparatus of claim 1,

wherein the pipeline front-end lacks capability to determine proper execution order for DCTI couples within fetched groups of instructions.

5. The computing apparatus of claim 1,

wherein the architecturally-defined special branching behavior includes a requirement that, for an instruction sequence that contains a DCTI couple, for which both branches are at least predicted taken, control is transferred briefly to the target of the first DCTI of the couple and then to the target of the second.

6. The computing apparatus of claim 1,

wherein the downstream pipeline section, upon detecting nested predicted taken DCTIs, is configured to determine proper instruction execution order and to cause the pipeline front-end to fetch additional instruction groups accordingly.

7. The computing apparatus of claim 1,

wherein the downstream pipeline section, upon detecting a second consecutive predicted taken DCTI, is configured to determine a proper next program counter (NPC) value and to cause the pipeline front-end to fetch a next instruction at an address indicated by the NPC.

8. The computing apparatus of claim 1,

wherein the downstream pipeline section, upon detecting a second consecutive predicted taken DCTI, is configured to step through a group of successive instructions until a predetermined number of consecutive instructions other than DCTIs are executed, by successively determining a next program counter (NPC) value for each stepped instruction and causing the pipeline front-end to fetch an instruction at an address indicated by the NPC.

9. The computing apparatus of claim 1, configured as a multiple instruction issue, in-order issue processor.

10. The computing apparatus of claim 1, further comprising:

multiple execution pipelines sharing the pipeline front-end, each execution pipeline comprising at least one fetch buffer for storing one or more groups of fetched instructions.

11. The computing apparatus of claim 1, embodied as a multi-core processor integrated circuit.

12. The computing apparatus of claim 1, embodied as one or more computer readable storage media encoding a design file representation of a processor integrated circuit.

13. The computing apparatus of claim 1, embodied as a computer system and further comprising:

a memory interface coupled to the instruction store; and

a memory hierarchy coupled to the memory interface.

14. A multi-core processor in which plural of the implemented cores share a front-end section that fetches instructions to be executed in functional units of the cores and that enforces an instruction set defined special branching behavior for program sequences that include a second delayed control transfer instruction (DCTI) in the delay slot of a first DCTI in commit logic rather than in fetch sequencing logic of the front-end section.

15. The multi-core processor of claim 14, further comprising:

an instruction store from which the front-end section fetches instructions.

16. The multi-core processor of claim 14,

wherein the front-end section fetches instructions generally without regard to the instruction set defined special branching behavior.

17. The multi-core processor of claim 14, in combination with, and coupled to, a memory hierarchy in which the first and second DCTIs span a cache line boundary.

18. A method of operating a processor configured to execute an instruction set that includes at least one delayed control transfer type instruction (DCTI), the method comprising:

fetching instructions from an instruction store generally without regard to an architecturally-defined special branching behavior for program sequences that include a second DCTI in the delay slot of a first DCTI;

speculatively executing instruction sequences including at least some subsequences that are inconsistent with the architecturally-defined special branching behavior; and

identifying in the speculatively executed instruction sequences, a subsequence containing the second DCTI in the delay slot of the first DCTI and enforcing the architecturally-defined special branching behavior.

19. The method of claim 18, further comprising:

selectively committing executed instructions to architectural state in a commit stage of the processor, the commit stage enforcing the architecturally-defined special branching behavior.

20. The method of claim 18, further comprising:

directing further fetching of instructions from the instruction store based on results of the post-speculative execution enforcement of the architecturally-defined special branching behavior.