SPEEDING UP DEFECT DIAGNOSIS TECHNIQUES

• US 20070226570A1
• Filed: 03/20/2007
• Published: 09/27/2007
• Est. Priority Date: 03/20/2006
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Cheng, Wu-Tung, Tang, Huaxing, Zou, Wei
• Granted Patent: US 8,812,922 B2
• Time in Patent Office: Days
• US Class Current: 714/741
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G06F 11/2252 using fault dictionaries
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to diagnose defects using compacted fail data produced by test response compactors. A dictionary of small size can be used to reduce the size of a fault candidate list and also to facilitate procedures to select a subset of passing patterns for simulation. Critical path tracing can be used to handle failing patterns with a larger number of failing bits, and a pre-computed small dictionary can be used to quickly find the initial candidates for failing patterns with a smaller number of failing bits. Also described herein are exemplary techniques for selecting passing patterns for fault simulation to identify faults in an electronic circuit.

Claims

1. A method of diagnosing defects in an electronic circuit, the method comprising:

determining a set of one or more fault candidates for the electronic circuit for a set of failing test patterns by using a fault dictionary that describes responses of one or more modeled faults to the failing test patterns;

simulating one or more fault candidates of the determined set using passing test patterns, failing test patterns, or both failing and passing test patterns; and

storing the one or more fault candidates and results of the simulating one or more fault candidates on one or more computer-readable media.

2. The method of claim 1, further comprising:

ranking the one or more fault candidates based at least in part on results of the simulation; and

storing the results of the ranking on one or more computer-readable media.

3. The method of claim 1, wherein the fault dictionary comprises one or more entries identifying one or more fault candidates and identifying one or more clocks that are associated with scan cells that capture failing bits caused by the one or more fault candidates.

4. The method of claim 1, wherein the fault dictionary comprises information associating one or more circuit clock signals with the one or more fault candidates.

5. The method of claim 1, wherein the fault dictionary comprises one or more entries indicating possible signatures produced by one or more of the failing test patterns.

6. One or more computer-readable media comprising instructions configured to cause a computer to perform the method of claim 1.

7. A method of diagnosing one or more defects in an electronic circuit, the method comprising:

determining a portion of a first list of candidate faults for one or more failing test patterns applied to the electronic circuit, the determination being made using a description of one or more modeled faults and circuit responses produced by the one or more modeled faults;

performing fault simulation of at least some of the candidate faults of the first list to determine a second list of candidate faults; and

storing at least one of the first or second lists in one or more computer-readable media.

8. The method of claim 7, wherein the portion of the first list is a first portion of the first list, the method further comprising determining a second portion of the first list of candidate faults using critical path tracing.

9. The method of claim 7, wherein the responses produced by the one or more modeled faults are signatures produced by compression hardware, the method further comprising generating the description by simulating the one or more modeled faults and determining the signatures produced by the one or more modeled faults when the one or more failing test patterns are applied.

10. One or more computer-readable media comprising instructions configured to cause a computer to perform the method of claim 7.

11. A method of diagnosing defects in an electronic circuit comprising two or more clocks, the method comprising:

selecting one or more passing test patterns for simulation with one or more fault candidates of the electronic circuit, wherein the passing test patterns are selected based at least in part on associations of the one or more passing test patterns with one or more clocks associated with the one or more fault candidates; and

storing the selection in one or more computer-readable media.

12. The method of claim 11, further comprising determining the associations of the patterns with one or more clocks based at least in part on a netlist description of the circuit.

13. The method of claim 11, wherein the associations indicate which of the two or more clocks clock scan cells that capture failing bits caused by the one or more fault candidates.

14. The method of claim 11, wherein an association of a respective one of the two or more clocks with the one or more fault candidates is indicated by a single bit.

15. One or more computer-readable media comprising instructions configured to cause a computer to perform the method of claim 11.

16. A method of generating a fault dictionary for use in diagnosing faults in an electronic circuit, the method comprising:

for a selected fault,

simulating one or more test patterns being applied to the electronic circuit in the presence of the selected fault;

determining test responses to the one or more test patterns that indicate the presence of the selected fault using the simulation; and

storing, in one or more computer-readable media, a fault dictionary entry that identifies the selected fault and identifies the test responses that indicate the presence of the selected fault.

17. The method of claim 16, wherein the fault dictionary entry is the only entry in the dictionary for the selected fault.

18. The method of claim 16, wherein the fault dictionary entry does not indicate which of the one or more test patterns caused the test responses that indicate the presence of the selected fault to be produced.

19. The method of claim 16, further comprising repeating the acts of simulating, determining, and storing for multiple additional faults.

20. The method of claim 16, wherein the act of determining the test responses comprises generating x-bit signatures from full test responses of the electronic circuit to the one or more test patterns.

21. The method of claim 20, wherein the act of storing the fault dictionary entry comprises storing the corresponding x-bit signatures as the test responses that indicate the presence of the selected fault.

22. The method of claim 21, wherein the x-bit signatures are generated by a simulated multiple-input signature register (MISR).

23. The method of claim 21, further comprising storing information indicative of which clocks clocked scan cells that captured failing bits indicative of the presence of the selected fault during the simulation.

24. One or more computer-readable media comprising instructions configured to cause a computer to perform the method of claim 16.

25. A method of generating a fault dictionary for use in diagnosing faults in an electronic circuit, the method comprising:

determining, for a selected fault, that a first test pattern and a second test pattern detect the selected fault and produce a same respective signature; and

storing in one or more computer-readable media one fault dictionary entry for the first and second failing test patterns.

26. The method of claim 25, wherein the approximate size of the fault dictionary corresponds to a size of a signature, a number of faults in the electronic circuit detectable by the one or more failing test patterns, an average number of unique signatures for faults, and a number of clocks in the electronic circuit.

27. The method of claim 25, wherein the act of determining comprises compacting test results from the first test pattern and the second test pattern.

28. The method of claim 25, wherein the act of determining comprises compacting test results of the one or more failing test patterns in a simulated multiple-input shift register.

29. A method of diagnosing one or more defects in an electronic circuit design using a fault dictionary made according to the method of claim 25.

30. One or more computer-readable media storing a fault dictionary made according to the method of claim 25.

31. One or more computer-readable media comprising instructions configured to cause a computer to perform the method of claim 25.

32. A method of generating a fault dictionary for diagnosing faults in an electronic circuit, the method comprising:

simulating one or more faults in a representation of the electronic circuit as one or more test patterns are applied to the representation;

selecting one or more failing test patterns from the simulation results;

identifying one or more unique failing bit combinations for the selected failing patterns;

creating one or more signatures from the one or more unique failing bit combinations; and

storing the one or more signatures in one or more computer-readable media.

33. The method of claim 32, wherein the act of selecting the one or more failing test patterns comprises selecting failing test patterns whose simulated results produce fewer than a threshold number of failing bits.

34. The method of claim 32, wherein the method is part of a preprocessing phase of an electronic circuit testing method.

35. The method of claim 32, wherein the storing the one or more signatures comprises associating a given signature with a group of two or more faults.

36. The method of claim 35, wherein the group of two or more faults is located in a fan-out free region.

37. One or more computer-readable media comprising a fault dictionary made according to the method of claim 32.

38. One or more computer-readable media comprising instructions configured to cause a computer to perform the method of claim 32.

39. A method of diagnosing one or more faults in an electronic circuit, the method comprising:

determining if a failing test pattern applied to the circuit comprises more than a threshold number of failing bits, wherein the threshold number is greater than one;

if the pattern does not comprise more than the threshold number of failing bits;

determining a signature for the failing test pattern;

determining one or more fault candidates associated with the signature using a dictionary; and

storing one or more of the fault candidates in one or more computer-readable media.

40. The method of claim 39, further comprising:

if the pattern comprises more than the threshold number of failing bits;

performing path tracing to determine one or more fault candidates; and

storing one or more of the fault candidates in one or more computer-readable media.

41. The method of claim 39, further comprising:

performing fault simulation for one or more of the fault candidates; and

storing results of the fault simulation in one or more computer-readable media.

42. The method of claim 39, wherein determining one or more fault candidates comprises determining two or more fault candidates, the determining two or more fault candidates comprising:

querying the dictionary with the signature;

receiving query results indicative of two or more fault candidates associated with the signature; and

determining the two or more fault candidates from the query results.

43. One or more computer-readable media comprising a fault dictionary made according to the method of claim 39.

44. One or more computer-readable media comprising instructions configured to cause a computer to perform the method of claim 39.