Virtual vector processing

• US 20070226735A1
• Filed: 03/22/2006
• Published: 09/27/2007
• Est. Priority Date: 03/22/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nguyen, Anthony, Kim, Daehyun, Smelyanskiy, Mikhail, Ipek, Engin, Lee, Victor
• Granted Patent: US 9,870,267 B2
• Time in Patent Office: Days
• US Class Current: 718/1
• CPC Class Codes: G06F 15/8053 Vector processors
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 9/5044 considering hardware capabilities

Abstract

Methods and apparatus to provide virtualized vector processing are described. In one embodiment, one or more operations corresponding to a virtual vector request are distributed to one or more processor cores for execution.

Claims

1. An apparatus comprising:

a first logic to allocate a first portion of one or more operations corresponding to a virtual vector request to a first processor core; and

a second logic to generate a first signal corresponding to a second portion of the one or more operations.

2. The apparatus of claim 1, further comprising a second processor core to receive the first signal, wherein the second processor core comprises:

a third logic to allocate a third portion of the one or more operations to the second processor core; and

a fourth logic to generate a second signal corresponding to a fourth portion of the one or more operations.

3. The apparatus of claim 2, wherein the third logic allocates the third portion based on information corresponding to one or more available resources of the second processor core.

4. The apparatus of claim 2, wherein the third logic allocates the third portion based on information corresponding to the first signal.

5. The apparatus of claim 2, further comprising a fourth logic to maintain information corresponding to one or more available resources of the second processor core.

6. The apparatus of claim 2, wherein the third logic allocates the third portion based on overhead information corresponding to communication with one or more of the first processor core or a third processor core.

7. The apparatus of claim 2, further comprising a fifth logic to transmit an acknowledgment signal to the first processor core after the second processor core has retired one or more operations corresponding to the third portion.

8. The apparatus of claim 1, wherein the first processor core comprises one or more of the first logic or the second logic.

9. The apparatus of claim 1, further comprising a plurality of processor cores.

10. The apparatus of claim 1, further comprising a third logic to maintain information corresponding to one or more available resources of the first processor core.

11. The apparatus of claim 1, wherein the first logic allocates the first portion based on information corresponding to one or more available resources of the first processor core.

12. The apparatus of claim 1, further comprising a second processor core to generate a second signal, wherein the first logic allocates the first portion based on information corresponding to the second signal.

13. The apparatus of claim 1, further comprising a third logic to schedule one or more tasks corresponding to the first portion.

14. The apparatus of claim 1, wherein the first logic allocates the first portion based on overhead information corresponding to communication with a second processor core.

15. The apparatus of claim 1, further comprising a memory to store one or more instructions corresponding to the virtual vector request.

16. The apparatus of claim 1, further comprising a third logic to aggregate a first computational result corresponding to the first portion and a second computational result corresponding to the second portion.

17. The apparatus of claim 1, wherein the first signal comprises data corresponding to one or more of an identifier of the first processor core, a starting value corresponding to the second portion, or an end value corresponding to the second portion.

18. A method comprising:

executing a first set of operations corresponding to a virtual vector instruction on a first processor;

generating a first signal corresponding to a second set of operations of the virtual vector instruction; and

executing at least a portion of the second set of operations on a second processor.

19. The method of claim 18, further comprising allocating the first set of operations based on information corresponding to one or more available resources of the first processor.

20. The method of claim 18, further comprising maintaining information corresponding to one or more available resources of one or more of the first processor or the second processor.

21. The method of claim 18, further comprising allocating the first set of operations based on overhead information corresponding to communication between the first processor and the second processor.

22. The method of claim 18, further comprising transmitting an acknowledgment signal to the first processor after the second processor has retired one or more operations corresponding to the second set of operations.

23. A system comprising:

a memory to store an instruction corresponding to one or more virtual vector operations; and

a first logic to distribute a first portion of the virtual vector operations and a second portion of the virtual vector operations for execution on a plurality of processors.

24. The system of claim 23, wherein at least one of to the plurality of processors comprises the first logic.

25. The system of claim 23, wherein the first logic selects one or more of the first or second portions based on information corresponding to one or more available resources of at least one of the plurality of processors.

26. The system of claim 23, further comprising a second logic to aggregate a first computational result corresponding to the first portion and a second computational result corresponding to the second portion.

27. The system of claim 23, further comprising a second logic to schedule one or more tasks corresponding to one or more of the first portion or the second portion.

28. The system of claim 23, wherein the first logic generates a first signal corresponding to the second portion, wherein the first signal comprises data corresponding to one or more of an identifier of at least one of the plurality of processors, a starting value corresponding to the second portion, or an end value corresponding to the second portion.

29. The system of claim 23, wherein the plurality of processors are on a same die.

30. The system of claim 23, further comprising an audio device.