VIRTUAL CORES AND HARDWARE-SUPPORTED HYPERVISOR INTEGRATED CIRCUITS, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE

• US 20070226795A1
• Filed: 02/06/2007
• Published: 09/27/2007
• Est. Priority Date: 02/09/2006
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Conti, Gregory, Petrosian, Levon, Hussain, Atif
• Application Number:
  US11/671,752
• Publication Number:
  US 20070226795A1
• Time in Patent Office: Days
• US Class Current: 726/22
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode

Abstract

An electronic system (1400) includes a processor (1422, 2610) having a pipeline, a bus (2655) coupled to the pipeline, a storage (1435, 1440, 2650) coupled to the bus (2655), the storage (1435, 2650) having a real time operating system (RTOS) and a real-time application, a non-real-time operating system (HLOS), a secure environment kernel (SE), and a software monitor (2310); and protective circuitry (2460) coupled to the processor and operable to establish a first signal (VP1_Active) and a second signal (NS) each having states and together having combinations of the states representing a first category (2430) for the real-time operating system and the real-time application, a second category (2420) for the non-real-time operating system, and a third category (2450) for the secure environment kernel.

Claims

1. An electronic device comprising

a processor including a pipeline operable to execute instructions in a real-time category or a non-real-time category, the processor operable in a secure or non-secure mode and in a monitor or a non-monitor mode and further operable to generate mode signals on a secure mode line and a monitor mode line;

a bus coupled to said pipeline for accesses; and

protective circuitry coupled to said processor, said protective circuitry having a register field operable to couple first and second qualifiers to said bus wherein the first qualifier is responsive to said secure mode line and the second qualifier represents whether the processor is in the real-time category or not for a given access, and said protective circuitry further responsive to the monitor mode line to permit alteration of said register field by said processor when the processor is in the monitor mode and to prevent alteration of at least part of said register field when said processor is in a non-monitor mode.

2. An integrated circuit comprising

a processor including a pipeline;

a bus coupled to said pipeline;

a storage coupled to said bus, said storage having a real time operating system, a non-real-time operating system, and a software monitor; and

a security circuit coupled to said bus and operable to generate at least one security violation signal unless a transition between the real time operating system and the non-real-time operating system includes the software monitor.

3. An electronic system comprising

a processor including a pipeline;

a bus coupled to said pipeline;

a storage coupled to said bus, said storage having a real time operating system and a real-time application, a non-real-time operating system, a secure environment kernel, and a software monitor; and

protective circuitry coupled to said processor and operable to establish a first signal and a second signal each having states and together having combinations of the states representing a first category for the real-time operating system and the real-time application, a second category for the non-real-time operating system, and a third category for the secure environment kernel.

4. A security circuit for use with a processor having modes and address signals, the security circuit comprising:

a security violation handler;

a first checker circuit having a first checker output coupled to said security violation handler and said first checker circuit having input lines for receiving mode signals indicative of at least some of the modes and said first checker circuit having logic circuitry coupled to the input lines to detect mode transitions between the modes and activate the first checker output upon detection of a mode transition contrary to a permitted transition policy for said logic circuitry; and

a second checker circuit having a second checker output coupled to said security violation handler, said second checker circuit having second input lines for receiving mode signals indicative of at least some of the modes, said second checker circuit further having third input lines for receiving the address signals, and said second checker circuit having second logic circuitry responsive to the mode signals and to said address signals to identify attempted transactions of different modes and activate the second checker output upon detection of an attempted transaction including an address and a mode contrary to a permitted transaction policy for said second logic circuitry.

5. A processor having modes for processing in privilege and non-privilege modes and for processing in a monitor mode, the processor comprising

a pipeline;

a storage having a field for representing privilege mode and monitor mode, and said monitor mode is a first privilege mode and said processor has a second privilege mode; and

a security circuit having a security storage having a first state wherein said processor is enabled in a non-secure mode and a second state wherein said processor is enabled in a secure mode, and said monitor mode is a type of secure mode, and said security circuit is further operable to generate a security violation signal if an attempt occurs in a mode other than the monitor mode to change a state of said security storage.

6. An integrated circuit comprising

a processor having modes for processing in privilege and non-privilege modes and for processing in a monitor mode, the processor including

a pipeline;

and

a first storage for representing that said process is in the monitor mode or not and for representing at least first and second other privilege modes besides the monitor mode;

and

the integrated circuit further comprising a security circuit coupled to said processor and including

a second storage having a first state wherein an exception trap by said processor into monitor mode is permitted and a second state wherein the exception trap into monitor mode is not permitted; and

a security violation handler operable when said second storage is in the second state that does not permit exception trap into monitor mode to generate a security violation signal if a transition pertaining to monitor mode occurs in said first storage.

7. An integrated circuit comprising:

a processor operable to assert a physical address and to establish secure and public modes and privileged modes including a particular privileged mode;

a bus for communicating the asserted physical address;

a modem peripheral coupled to said bus to receive the asserted physical address; and

a security circuit coupled to said bus and operable to activate a qualifier signal indicative of modem operation by determining whether the asserted physical address lies within a predetermined address range for modem operation and has occurred in a public mode and in the particular privileged mode.

8. An electronic system comprising:

a processor operable to assert a physical address and to establish modes including modes that are privileged or non-privileged, and secure or public;

a bus for communicating the asserted physical address;

a system peripheral coupled to said bus to receive the asserted physical address;

a security circuit coupled to said bus and operable to activate qualifier signals including a system qualifier indicative of a category of processor operation representing a virtual processor in response to the physical address and modes; and

a firewall circuit for granting and denying access to said system peripheral in response to different states of the qualifier signals including the states of the system qualifier.

9. A processor for processing a software program and a software monitor, the processor comprising

a pipeline;

a storage having a first state wherein the pipeline is enabled to process the software program and said storage having a second state establishing a monitor mode wherein the pipeline is enabled to process the software monitor;

a bus coupled to said pipeline;

security circuit coupled to said bus and to said storage and operable to generate a security violation signal in response to an attempted access on said bus by said pipeline outside a predetermined address space when said storage has said second state establishing the monitor mode.

10. A processor having modes, the processor comprising

a pipeline;

a security zone mechanism operable according to its own axioms for permissible and impermissible operations pertaining to the various modes; and

a security circuit coupled with said security zone mechanism to further restrict at least one of the permissible operations to be impermissible.

11. An electronic circuit comprising:

a processor having modes including a high-level control mode;

peripherals coupled to said processor;

power management circuitry dividing and controlling the electronic circuit in power domains with power events of power-up and power-down to the power domains; and

a security circuit having a platform status register coupled with said power domains to detect a power event and to interrupt said processor to said high-level control mode to protect information security of the electronic circuit.

12. A processor for processing a software program and a software monitor and a predetermined address space reserved for said software monitor, the processor comprising

a pipeline;

a storage having a first state wherein the pipeline is enabled to process the software program and said storage having a second state establishing a monitor mode wherein the pipeline is enabled to process the software monitor;

a bus coupled to said pipeline;

a security circuit coupled to said bus and to said storage and operable to generate a security violation signal in response to an attempted access on said bus by said pipeline inside the predetermined address space reserved for said software monitor when said storage has said first state.

13. An electronic circuit comprising

a processor including a pipeline and a register circuit for modes including a monitor mode;

a bus coupled to said pipeline;

a storage coupled to said bus, said storage having a real time operating system and a non-real-time operating system;

an interrupt handler circuit coupled to said processor and operable to provide a first type of interrupt request and a second type of interrupt request, said processor responsive to said second type of interrupt request to activate the monitor mode; and

a pre-emptive masking handler circuit coupled to said processor and to said interrupt handler circuit so that said interrupt handler circuit is responsive to mask at least one non-real-time interrupt request and responsive to provide at least one real-time interrupt request of the second type to said processor.

14. An electronic system comprising

a processor including a plurality of processor cores each including a pipeline operable to execute instructions, at least one of said processor cores operable as a control core in a secure or non-secure mode and in a monitor or a non-monitor mode and further operable to generate mode signals on a secure mode line and a monitor mode line;

a bus coupled to said pipeline for accesses; and

protective circuitry coupled to said processor, said protective circuitry operable to couple a first qualifier to said bus wherein the first qualifier is responsive to said secure mode line, the protective circuitry further having a register field coupled to said bus, the register field acting as a second qualifier for representing which of said processor cores is active for a given access, and said protective circuitry further responsive to the monitor mode line to permit alteration of said register field by said processor when said control core is in the monitor mode and to prevent such alteration when said control core is in a non-monitor mode.

15. A process of manufacturing an electronic product, the process comprising:

fabricating in a wafer fabrication facility an integrated circuit having a processor operable for executing a hypervisor responsive to at least one interrupt, and having a secure hardware-supported hypervisor protective circuitry having configuration registers and firewalls; and

testing the integrated circuit by operating the processor and secure hardware-supported hypervisor protective circuitry while using the registers in at least two different configurations and verifying the hardware supported hypervisor, firewalls and interrupt operation pertaining to real-time and non-real-time operations.

16. An electronic assembly comprising:

a first integrated circuit including an application processor operable to execute a hypervisor and at least one operating system selected from the group consisting of a real-time operating system, a non-real-time operating system, and a secure environment kernel, and the first integrated circuit including a protective circuitry coupled to said processor and operable to establish a first signal and a second signal each having states and together having combinations of the states representing a first category for the real-time operating system, a second category for the non-real-time operating system, and a third category for the secure environment kernel; and

a second integrated circuit physically affixed and communicatively coupled to said application processor and to said protective circuitry of said first integrated circuit, said second integrated circuit including a second processor operable to execute at least one additional operating system selected from the group consisting of a real-time operating system, a non-real-time operating system, and a secure environment kernel.

17. A telecommunications unit comprising:

a processor including a pipeline;

a bus coupled to said pipeline;

a storage coupled to said bus, said storage having a real time operating system and a real-time modem application, a non-real-time operating system, a secure environment kernel, and a software monitor;

protective circuitry coupled to said processor and operable to establish a first signal and a second signal each having states and together having combinations of the states representing a first category for the real-time operating system and the real-time application, a second category for the non-real-time operating system, and a third category for the secure environment kernel;

a telecommunications modem circuit coupled to said processor; and

a user interface coupled to said processor.