METHODS OF PROGRAMMING NON-VOLATILE MEMORY DEVICES INCLUDING TRANSITION METAL OXIDE LAYER AS DATA STORAGE MATERIAL LAYER AND DEVICES SO OPERATED

• US 20070228370A1
• Filed: 06/13/2007
• Published: 10/04/2007
• Est. Priority Date: 11/23/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Baek, In-Gyu, Lee, Moon-Sook
• Granted Patent: US 7,480,174 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/026 by physical vapor deposition, e.g. sputtering
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A method of programming a non-volatile memory device including a transition metal oxide layer includes applying a first electric pulse to the transition metal oxide layer for a first period to establish a resistance of the transition metal oxide layer and applying a second electric pulse to the transition metal oxide layer for a second period, longer than the first period, to increase the resistance of the transition metal oxide layer. Related devices are also disclosed.

Claims

1-20. -20. (canceled)

21. A method of programming a memory device including a data storage material layer, the method comprising:

applying a first electric pulse to the data storage material layer for a first period to reduce a resistance of the data storage material layer; and

applying a second electric pulse to the data storage material layer for a second period, longer than the first period, to increase the resistance of the data storage material layer.

22. The method according to claim 21 further comprising:

applying at least a third electric pulse after the second electric pulse to the data storage material layer for a third period, longer than the first period, to increase a resistance of the data storage material layer.

23. The method according to claim 21, wherein applying a first electric pulse comprises applying a voltage that is greater than the voltage of the second electric pulse.

24. A memory device comprising:

a lower electrode on a substrate;

an upper electrode on the lower electrode; and

a data storage material layer between the lower electrode and the upper electrode configured to provide relatively high resistance responsive to a first electric pulse applied to the data storage material layer for a first period and to provide a relatively low resistance responsive to a second electric pulse applied to the data storage material layer for a second period, longer than the first period.

25. The memory device according to claim 24, wherein the data storage material layer comprises a material having a chemical formula, M_xO_y, where M comprises a transition metal comprising nickel, niobium, titanium, zirconium, hafnium, cobalt, iron, copper, and/or chrome.