3-DIMENSIONAL INTEGRATED CIRCUIT ARCHITECTURE, STRUCTURE AND METHOD FOR FABRICATION THEREOF
First Claim
1. An integrated circuit architecture comprising:
- a first array of first memory devices disposed on a first substrate layer, the first memory devices having a first power and performance specification;
a second array of second memory devices different from the first array disposed on a second substrate layer different from the first substrate layer, the second memory devices having a second power and performance specification different from the first power and performance specification; and
a plurality of logic devices disposed on a third substrate layer, the plurality of logic devices being coupled to the first array and the second array.
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Abstract
An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.
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Citations
20 Claims
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1. An integrated circuit architecture comprising:
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a first array of first memory devices disposed on a first substrate layer, the first memory devices having a first power and performance specification;
a second array of second memory devices different from the first array disposed on a second substrate layer different from the first substrate layer, the second memory devices having a second power and performance specification different from the first power and performance specification; and
a plurality of logic devices disposed on a third substrate layer, the plurality of logic devices being coupled to the first array and the second array. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit structure comprising:
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a first array of first memory devices located on a first substrate layer, the first memory devices having a first power and performance specification;
a second array of second memory devices different from the first array located on a second substrate layer different from the first substrate layer, the second memory devices having a second power and performance specification different from the first power and performance specification; and
a plurality of logic devices located on a third substrate layer, the plurality of logic devices being coupled to the first array and the second array. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A method for fabricating an integrated circuit comprising:
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forming a first array of first memory devices on a first substrate layer, the first memory devices having a first power and performance specification;
forming a second array of second memory devices different from the first array on a second substrate layer different from the first substrate layer, the second memory devices having a second power and performance specification different from the first power and performance specification;
forming a plurality of logic devices on a third substrate layer; and
coupling the first array, the second array and the plurality of logic devices. - View Dependent Claims (17, 18, 19, 20)
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Specification