SELF-ALIGNED COMPLEMENTARY LDMOS

• US 20070228463A1
• Filed: 04/02/2007
• Published: 10/04/2007
• Est. Priority Date: 04/03/2006
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Cai, Jun
• Application Number:
  US11/695,199
• Publication Number:
  US 20070228463A1
• Time in Patent Office: Days
• US Class Current: 257/343
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low threshold voltage version with a thin gate oxide on the source side of the device and a high threshold voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA, to reduce the device size and to reduce the device leakage.

Claims

1. A self-aligned LDMOS device, comprising:

a gate having a gate oxide, and an oxide spacer on a source side of said gate;

a source region having a tap and a source spacer embedded in a source well, the tap being aligned with an edge of the oxide spacer and the source spacer being aligned with the edge of the gate polysilicon such that the source spacer is fully under the oxide spacer; and

a drain region situated opposite to the source side of said gate, the drain region having a drain embedded in a drain well.

2. The self-aligned LDMOS device of claim 1, the gate comprising a second oxide spacer on the drain side of said gate, the drain being aligned with an edge of the second oxide spacer.

3. The self-aligned LDMOS device of claim 1, the tap and the source well comprising a P type dopant and the source spacer, the drain, and the drain well comprising an N type dopant.

4. The self-aligned LDMOS device of claim 1, the tap and the source well comprising an N type dopant and the source spacer, the drain, and the drain well comprising a P type dopant.

5. The self-aligned LDMOS device of claim 4, further comprising a complementary transistor having a complementary gate, a complementary source region, and a complementary drain region.

6. The self-aligned LDMOS device of claim 5, the complementary source region comprising a P type tap and a P type source well;

and the drain region comprising an N type source spacer, an N type drain, and an N type drain well.

7. The self-aligned LDMOS device of claim 1, the gate oxide being thick along substantially the entire cross-section of said gate.

8. The self-aligned LDMOS device of claim 1, the gate oxide being thin proximate to said source and thick proximate to said drain.

9. The self-aligned LDMOS device of claim 8, further comprising a second transistor gate with a second transistor gate oxide that is thick along substantially the entire cross-section of said second transistor gate.

10. The self-aligned LDMOS device of claim 1, further comprising an isolation ring surrounding the gate, source, and drain regions.

11. The self-aligned LDMOS device of claim 10, further comprising a field oxide extending from the isolation region to the source region on the source side of the gate.

13. The self-aligned LDMOS device of claim 8, further comprising an isolation ring surrounding the gate, source, and drain regions.

14. The self-aligned LDMOS device of claim 13, further comprising a field oxide extending from the isolation region to the source region on the source side of the gate.

15. The self-aligned LDMOS device of claim 14, further comprising a high voltage N well extending laterally from the isolation ring to the source well on the source side of the gate.

16. The self-aligned LDMOS device of claim 1, further comprising a field oxide extending from the gate oxide to the drain, and the gate having a polysilicon layer above the field oxide which extends laterally toward the drain to a location on the field oxide.

17. The self-aligned LDMOS device of claim 16, wherein the drain well extends laterally under the field oxide.

18. The self-aligned LDMOS device of claim 8, further comprising a field oxide extending from the gate oxide to the drain, and the gate having a polysilicon layer above the field oxide which extends laterally toward the drain to a location on the field oxide.

19. The self-aligned LDMOS device of claim 18, wherein the drain well extends laterally under the field oxide.

12. The self-aligned LDMOS device of claim 12, further comprising a high voltage N well extending laterally from the isolation ring to the source well on the source side of the gate.

20. A self-aligned LDMOS device, comprising:

a gate situated on a high voltage well, the gate having a gate oxide on the high voltage well and a polysilicon layer on the gate oxide;

a source region in the high voltage well on a source side of said gate;

a drain region in the high voltage well on a drain side of said gate; and

wherein the gate oxide is thick on the drain side of said gate.

21. The self-aligned LDMOS device of claim 21, the thick gate oxide having a thickness selected from the group consisting of about 400 Å

and 600 Å

.

22. The self-aligned LDMOS device of claim 21, the gate oxide being thick on the source side of said gate.

23. The self-aligned LDMOS device of claim 21, the gate being a split gate with a thin gate oxide on the source side.

24. The self-aligned LDMOS device of claim 23, the thin gate oxide having a thickness selected from the group consisting of about 45 Å

, about 60 Å

, and about 115 Å

.

25. The self-aligned LDMOS device of claim 21, said gate comprising an oxide spacer on the source side and said source region comprising a source that is fully under the oxide spacer.

26. A method of forming a self-aligned LDMOS device, comprising the steps of:

a) providing a high voltage well with an oxide layer and a polysilicon layer;

b) etching the oxide layer and the polysilicon layer to form a source region and a drain region with a gate therebetween;

c) forming a source well in the source region of the high voltage well and a drain well in the drain region of the high voltage well;

d) implanting a source body in the source region extending from the source well under the gate;

e) implanting a source in the source well; and

f) forming an oxide spacer over the source an adjacent the gate such that the oxide spacer fully covers the source.

27. The method of claim 26, further comprising the step of implanting a tap in the source well subsequent to said oxide spacer forming step.

28. The method of claim 27, further comprising the step of implanting a drain in the drain well.

29. The method of claim 28, further comprising the step of forming a silicide layer in the source region and the drain region, the source silicide layer contacting the tap and the source.

30. The method of claim 29, further comprising the addition of contacts to each of the source and the drain.

31. The method of claim 26, the source body and the source being aligned with an edge of the gate and formed using the same mask.

32. The method of claim 26, the source body and the source being implanted at an angle other than vertical.

33. The method of claim 26, the thickness of the oxide layer being one of the group consisting of about 45 Å

, about 60 Å

, about 115 Å

about 400 Å and

about 600 Å

.

34. The method of claim 26, the gate being a split gate with a thin gate oxide proximate the source region and a thick gate oxide proximate the drain region.