Charge balance techniques for power devices

• US 20070228490A1
• Filed: 03/30/2006
• Published: 10/04/2007
• Est. Priority Date: 03/30/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kocon, Christopher
• Granted Patent: US 7,592,668 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A charge balance semiconductor power device includes an active area comprising a plurality of cells capable of conducting current when biased in a conducting state. A non-active perimeter region surrounds the active area, wherein no current flows through the non-active perimeter when the plurality of cells is biased in a conducting state. Alternately arranged strips of p pillars and strips of n pillars extend through both the active area and the non-active perimeter region along a length of a die housing the semiconductor power device.

Claims

1. A charge balance semiconductor power device, comprising:

an active area comprising a plurality of cells capable of conducting current when biased in a conducting state;

a non-active perimeter region surrounding the active area, wherein no current flows through the non-active perimeter region when the plurality of cells are biased in the conducting state; and

alternately arranged strips of first conductivity type pillars and strips of second conductivity type pillars formed in a silicon region of the second conductivity type, the alternately arranged strips of first and second conductivity type extending through both the active area and the non-active perimeter region along a first dimension.

2. The charge balance semiconductor power device of claim 1 wherein each of the strips of first conductivity type pillars includes a discontinuity forming a portion of a strip of second conductivity type region, the strip of second conductivity type region extending in the non-active perimeter region perpendicular to the first dimension.

3. The charge balance semiconductor power device of claim 1 wherein each of the strips of first conductivity type pillars includes a plurality of discontinuities forming portions of a plurality of strips of second conductivity type regions, the plurality of strips of second conductivity type regions extending in the non-active perimeter region perpendicular to the first dimension.

4. The charge balance semiconductor power device of claim 1 wherein the charge balance semiconductor power device is a vertically-conducting power device.

5. The charge balance semiconductor power device of claim 1 wherein the first conductivity type is p type and second conductivity type is n type.

6. The charge balance semiconductor power device of claim 1 further comprising a field plate in the non-active termination region.

7. The charge balance semiconductor power device of claim 1 wherein the non-active perimeter region comprises a plurality of rings of the second conductivity type extending around the active area.

8. The charge balance semiconductor power device of claim 1 further comprising a field plate conductor extending into the non-active perimeter region, wherein a portion of the filed plate conductor is insulated from underlying strips of first conductivity type pillars and strips of second conductivity type pillars by a dielectric layer.

13. The charge balance semiconductor power device of claim 1 further comprising a field plate conductor extending into the non-active perimeter region, wherein a portion of the filed plate conductor is insulated from underlying strips of first conductivity type pillars and strips of second conductivity type pillars by a dielectric layer.

9. A vertically-conducting charge balance semiconductor power device, comprising:

an active area comprising a plurality of cells capable of conducting current when biased in a conducting state;

a non-active perimeter region surrounding the active area, wherein no current flows through the non-active perimeter region when the plurality of cells are biased in the conducting state; and

alternately arranged strips of first conductivity type pillars and strips of second conductivity type pillars extending through both the active area and the non-active perimeter region along a first dimension, each of the strips of first conductivity type pillars including a discontinuity forming a portion of a strip of second conductivity type region, the strip of second conductivity type region extending in the non-active perimeter region perpendicular to the first dimension.

10. The charge balance semiconductor power device of claim 9 wherein the first conductivity type is p type and second conductivity type is n type.

11. The charge balance semiconductor power device of claim 9 further comprising a field plate in the non-active termination region.

12. The charge balance semiconductor power device of claim 9 wherein the non-active perimeter region comprises a plurality of rings of the second conductivity type extending around the active area.

14. A charge balance semiconductor power device, comprising:

an active area comprising a plurality of cells capable of conducting current when biased in a conducting state;

a non-active perimeter region surrounding the active area, wherein no current flows through the non-active perimeter region when the plurality of cells are biased in the conducting state; and

strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending through both the active area and the non-active perimeter region along a length of a die housing the semiconductor power device, each of the strips of p pillars including a plurality of discontinuities forming portions of a plurality of strips of n regions, the plurality of strips of n regions extending in the non-active perimeter region perpendicular to the length of the die.

15. The charge balance semiconductor power device of claim 14 wherein the charge balance semiconductor power device is a vertically-conducting power device.

16. The charge balance semiconductor power device of claim 14 further comprising a field plate in the non-active termination region.

17. The charge balance semiconductor power device of claim 14 wherein the non-active perimeter region comprises a plurality of rings of the second conductivity type extending around the active area.

18. The charge balance semiconductor power device of claim 14 further comprising a field plate conductor extending into the non-active perimeter region, wherein a portion of the filed plate conductor is insulated from underlying strips of first conductivity type pillars and strips of second conductivity type pillars by a dielectric layer.

19. A silicon wafer comprising:

a silicon region of first conductivity type; and

a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from a location along a perimeter of the silicon wafer to an opposing location along the perimeter of the silicon wafer, the plurality of strips of second conductivity type pillars extending to a predetermined depth within the silicon region.

20. The silicon wafer of claim 19 wherein the first conductivity type is n type and second conductivity type is p type.

21. A silicon die comprising:

a silicon region of first conductivity type; and

a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from one edge of the silicon die to an opposing edge of the silicon die, the plurality of strips of second conductivity type pillars extending to a predetermined depth within the silicon region.

22. The silicon wafer of claim 21 wherein the first conductivity type is n type and second conductivity type is p type.

23. A method of forming a charge balance structure in a semiconductor die having a silicon region of first conductivity type, the method comprising:

forming a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from one edge of the silicon die to an opposing edge of the silicon die, the plurality of strips of second conductivity type pillars extending to a predetermined depth within the silicon region.

24. The silicon wafer of claim 23 wherein the forming step comprises:

forming a plurality of trenches extending to the predetermined depth in the silicon region, the trenches extending from the one edge of the silicon die to the opposing edge of the silicon die; and

filling the plurality of trenches with silicon material of the second conductivity type.

25. The method of claim 23 wherein the first conductivity type is n type and second conductivity type is p type.