Power device with improved edge termination

• US 20070228518A1
• Filed: 03/31/2006
• Published: 10/04/2007
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yilmaz, Hamza, Calafut, Daniel
• Granted Patent: US 7,521,773 B2
• Time in Patent Office: Days
• US Class Current: 257/551
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A field effect transistor includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and the resistive element is configured to induce a portion of the avalanche current to flow through the termination region and a remaining portion of the avalanche current to flow through the active region.

Claims

1. A field effect transistor comprising:

an active region;

a termination region surrounding the active region; and

a resistive element coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and the resistive element is configured to induce a portion of the avalanche current to flow through the termination region and a remaining portion of the avalanche current to flow through the active region.

2. The field effect transistor of claim 1 wherein the termination region includes a termination well of a first conductivity type extending to a first depth within a drift region of a second conductivity type, and the active region includes an active well of the first conductivity type extending to a second depth within the drift region, the first depth being deeper than the second depth.

3. The field effect transistor of claim 2 wherein the termination well forms one end of the resistive element, and the other end of the resistive element is biased to ground potential during operation.

4. The field effect transistor of claim 2 wherein the termination well forms a ring surrounding the active region, the termination well comprising a plurality of discontinuous well contact regions intermittently placed around the active region, the plurality of well contact regions being of the first conductivity type.

5. The field effect transistor of claim 2 further comprising:

a first interconnect layer extending over the active region and a portion of the termination region; and

a second interconnect layer configured to electrically connect the termination well to the first interconnect layer, wherein the second interconnect layer has a lower conductivity than the first interconnect layer.

6. The field effect transistor of claim 5 wherein the first interconnect layer comprises metal, and the second interconnect layer comprises polysilicon.

7. The field effect transistor of claim 1 wherein the active region includes charge balanced structures.

8. The field effect transistor of claim 1 wherein the active region includes a plurality of shielded gate trench power MOSFET cells.

9. The field effect transistor of claim 1 further comprising:

an interconnect layer having a first portion extending over the active region and a second portion extending over the termination region; and

a dielectric layer partially insulating the first and second portions of the interconnect layer from one another, the second portion of the interconnect layer forming a part of the resistive element.

10. The field effect transistor of claim 9 wherein the second portion of the interconnect layer serves as a filed plate extending over the termination region.

11. The field effect transistor of claim 1 wherein the resistive element has a value in the range of 1 kΩ

*μ

m to 1 mega-Ω

*μ

m.

12. The field effect transistor of claim 1 wherein during operation, one end of the resistive element is biased to ground potential.

13. A trench gate power MOSFET comprising:

a drift region of a first conductivity type over a substrate of the first conductivity type;

an active region comprising;

an active well of a second conductivity type extending to a predetermined depth within the drift region;

a plurality of gate trenches extending through the well region; and

a plurality of source regions of the first conductivity type flanking sides of the plurality of gate trenches;

a termination region surrounding the active region, comprising;

a termination well of the second conductivity type extending deeper into the drift region than the active well; and

a resistive element coupled to the termination well, wherein during a UIL switching event upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and when the avalanche current reaches a predetermined level the resistive element induces a portion of the avalanche current to flow through the active region and a remaining portion of the avalanche current to flow through the termination region.

14. The field effect transistor of claim 13 wherein the termination well forms one end of the resistive element, and the other end of the resistive element is biased to ground potential during operation.

15. The field effect transistor of claim 13 wherein the termination well forms a ring surrounding the active region, the termination well comprising a plurality of discontinuous well contact regions intermittently placed around the active region, the plurality of well contact regions being of the first conductivity type.

16. The field effect transistor of claim 13 further comprising:

a first interconnect layer extending over the active region and a portion of the termination region; and

a second interconnect layer configured to electrically connect the termination well to the first interconnect layer, wherein the second interconnect layer has a lower conductivity than the first interconnect layer.

17. The field effect transistor of claim 16 wherein the first interconnect layer comprises metal, and the second interconnect layer comprises polysilicon.

18. The field effect transistor of claim 13 further comprising:

an interconnect layer having a first portion extending over the active region and a second portion extending over the termination region; and

a dielectric layer partially insulating the first and second portions of the interconnect layer from one another, the second portion of the interconnect layer forming a part of the resistive element.

19. The field effect transistor of claim 18 wherein the second portion of the interconnect layer serves as a filed plate extending over the termination region.

20. The field effect transistor of claim 13 wherein the resistive element has a value in the range of 1 kΩ

*μ

m to 1 mega-Ω

*-82 m.

21. The field effect transistor of claim 13 wherein during operation, one end of the resistive element is biased to ground potential.

22. The semiconductor device of claim 13 wherein the termination region further includes a termination trench extending into the drift region adjacent to the termination well, the termination trench surrounding the active region in the shape of a ring.

23. The field effect transistor of claim 13 wherein each gate trench comprises:

a shield electrode insulated from the drift region by a shield dielectric; and

a gate electrode over but insulated from the shield electrode by an inter-poly dielectric layer.

24. The field effect transistor of claim 13 wherein each gate trench comprises:

a gate dielectric lining the gate trench sidewalls;

a bottom dielectric thicker than the gate dielectric, lining the gate trench bottom; and

a recessed gate electrode over the bottom dielectric.

25. A field effect transistor comprising:

an active region;

a termination region surrounding the active region;

a resistive means coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and when the avalanche current reaches a predetermined level the resistive means operates to induce a portion of the avalanche current to flow through the termination region and a remaining portion of the avalanche current to flow through the active region.

26. The field effect transistor of claim 25 wherein the termination region includes a termination well of first conductivity type extending to a first depth within a drift region of a second conductivity type.

27. The field effect transistor of claim 26 wherein the termination well forms one end of the resistive means, and the other end of the resistive means is biased to ground potential during operation.

28. The field effect transistor of claim 26 wherein the termination well forms a ring surrounding the active region, the termination well comprising a plurality of discontinuous well contact regions intermittently placed around the active region, the plurality of well contact regions being of the first conductivity type.

29. The field effect transistor of claim 25 further comprising:

a first interconnect layer extending over the active region and a portion of the termination region; and

a second interconnect layer configured to electrically connect the termination well to the first interconnect layer, wherein the second interconnect layer has a lower conductivity than the first interconnect layer.

30. The field effect transistor of claim 25 further comprising:

an interconnect layer having a first portion extending over the active region and a second portion extending over the termination region; and

a dielectric layer partially insulating the first and second portions of the interconnect layer from one another, the second portion of the interconnect layer forming a part of the resistive means.

31. The field effect transistor of claim 25 wherein during operation, one end of the resistive means is biased to ground potential.