Controlling Flip-Chip Techniques for Concurrent Ball Bonds in Semiconductor Devices

• US 20070228543A1
• Filed: 06/08/2006
• Published: 10/04/2007
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Gerber, Mark A., Walter, David N., Le, Duy-Loan T.
• Granted Patent: US 7,573,137 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4845 Details of ball bonds
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48647 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/8121 : using a reflow oven
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/85045 : using a corona discharge, e.g. electronic flame off [EFO]
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06579 : TAB carriers; beam leads
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/20105 : Temperature range 150 C=<T<200 C, 423.15 K =< T < 473.15K
• CPC Class Codes: H01L 2924/20106 : Temperature range 200 C=<T<250 C, 473.15 K =<T < 523.15K
• CPC Class Codes: H01L 2924/20107 : Temperature range 250 C=<T<300 C, 523.15K =<T< 573.15K
• CPC Class Codes: H01L 2924/20751 : larger or equal to 10 microns less than 20 microns
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/20754 : larger or equal to 40 microns less than 50 microns
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns
• CPC Class Codes: H01L 2924/20756 : larger or equal to 60 microns less than 70 microns
• CPC Class Codes: H01L 2924/20757 : larger or equal to 70 microns less than 80 microns
• CPC Class Codes: H01L 2924/20758 : larger or equal to 80 microns less than 90 microns
• CPC Class Codes: H01L 2924/20759 : larger or equal to 90 microns less than 100 microns

Abstract

A device has a first semiconductor chip (101) with contact pads in an interior first set (102) and a peripheral second set (103). A deformed sphere (104) of non-reflow metal such as gold is placed on each contact pad of the first and second sets. At least one additional deformed sphere (105) is placed on the first set pads, forming column-shaped spacers. The first chip is attached to a substrate (110) with a chip attachment location and a third set of contact pads (112) near the location. Low profile bond wires (130) span between the pads of the third set and the second set. A second semiconductor chip (140) of a size has a fourth set of contact pads (141) at locations matching the first set pads. The second chip is placed over the first chip so that the fourth set pads are aligned with the spacers on the matching first set pads, and at least one edge of the second chip overhangs the sphere on at least one pad of the second set. A reflow metal (142) bonds the spacers to the second chip, while the spacers space the first and second chips by a gap (105a) wide enough for placing the wire spans to the second set pads.

Claims

1. A semiconductor device comprising:

a first semiconductor chip having a size and an active and a passive surface, the active surface including an interior first set and a peripheral second set of contact pads at pad locations;

a deformed sphere of non-reflow metal placed on the contact pads of the first and second sets;

at least one additional deformed sphere placed on the spheres of the first set pads, forming column-shaped spacers having a height;

a substrate having a first surface with an attachment location and a third set of contact pads near the location;

the passive surface of the first chip attached to the substrate attachment location;

low-profile bond wire spans between the pads of the third set and the second set to electrically connect the substrate and the first chip, the profile being lower than the height of the spacers;

a second semiconductor chip having a second size and a fourth set of contact pads at locations matching the first set;

the second chip placed over the first chip and the fourth set pads aligned with the spacers on the matching first set pads; and

a reflow metal on the fourth set pads bonding to the spacers, connecting the second and first chips, at least one edge of the second chip overhanging the sphere on at least one pad of the second set.

2. The device according to claim 1 wherein the deformed spheres have about equal size.

3. The device according to claim 1 wherein the non-reflow metal includes gold.

4. The device according to claim 1 wherein the second chip has a size approximately equal to the first chip size.

5. The device according to claim 1 further including a polymer material to fill the gap between the first and second chips.

6. The device according to claim 5 wherein the polymer material includes a precursor based on an epoxy and polyimide compound.

7. The device according to claim 1 wherein the substrate is a third semiconductor chip.

8. The device according to claim 7 further including reflow bodies attached to the substrate surface opposite to its first surface to provide connection to external parts.

9. The device according to claim 1 further including an encapsulation of the third set pads and the connecting bond wires in protective material.

10. A method for fabricating a semiconductor device comprising the steps of:

providing a first chip having a size, an active and a passive surface, the active surface including devices having an interior first set and a peripheral second set of contact pads;

providing a substrate having a first surface with an attachment location and a third set of contact pads near the location;

attaching the passive surface of the first chip onto the attachment location of the substrate;

placing and squeezing squeezed a gold ball on each contact pad of the first and second sets;

repeating the ball placing and squeezing for the pads of the first set to create column-shaped spacers of a height;

spanning low profile wire bonds between the pads of the second and the third sets to electrically connect the first chip and the substrate, the profile being lower than the height of the spacers;

providing a second semiconductor chip having a second size and devices with a fourth set of contact pads at locations matching the first pad set;

applying reflow metal to the pads of the fourth set, or to the spacers, or to both;

placing the second chip over the first chip and aligning the fourth set pads with the spacers on the matching first set pads so that at least one edge of the second chip overhangs the ball on at least one pad of the second set; and

applying thermal energy to reflow the metal for bonding the fourth set pads to the spacers on the first set pads, electrically connecting the first and the second chip.

11. The method according to claim 10 further including, after the step of spanning the wire bonds, the step of depositing a polymer precursor material over the active surface of the first chip in a height about equal to the spacer height, protecting the bonds on the second set pads.

12. The method according to claim 10 further including the step of encapsulating the wire bonds and at least a portion of the substrate in a protective material.

13. The method according to claim 10 wherein the substrate is a third semiconductor chip.

14. The method according to claim 10 wherein the substrate has an insulating body integral with conductive lines and vias.

15. The method according to claim 10 wherein the squeezed gold ball is a free air ball in gold wire bonding.

16. The method according to claim 15 wherein the repeated gold ball placings are produced from free air balls in gold wire bonding so that the squeezed balls have about equal size and are bonded together to form a column-shaped spacer.

17. The method according to claim 16 wherein the repeated placings produce spacers of about the same height so that the first and the second chip are spaced by substantially uniform distance.

18. The method according to claim 10 wherein the wires between the pads of the second and the third set are placed so that the ball is attached to the pad of the third set and the stitch is attached to the previously placed squeezed ball on the pad of the second set.

19. The method according to claim 10 further including the step of attaching reflow bodies to the substrate surface opposite its first surface to provide connection to external parts, the melting temperature of the reflow bodies lower than the melting temperature of the reflow metal employed on the fourth set pads.