Class ab folded cascode stage and method for low noise, low power, low-offset operational amplilier

• US 20070229156A1
• Filed: 04/03/2006
• Published: 10/04/2007
• Est. Priority Date: 04/03/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Alenin, Sergey, Surtihadi, Henry
• Granted Patent: US 7,411,451 B2
• Time in Patent Office: Days
• US Class Current: 330/252
• CPC Class Codes: H03F 2203/45212 the differential amplifier being designed to have a reduced offset
• CPC Class Codes: H03F 2203/45302 the common gate stage of a cascode dif amp being controlled
• CPC Class Codes: H03F 2203/45431 the CMCL output control signal being a current signal
• CPC Class Codes: H03F 2203/45512 the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45652 the LC comprising one or more further dif amp stages, either identical to the dif amp or not, in cascade
• CPC Class Codes: H03F 3/45291 Folded cascode stages
• CPC Class Codes: H03F 3/45896 by using a feedback circuit

Abstract

An amplifier circuit includes an pair of input transistors, the drains of which are connected to emitters of first and second cascode transistors. First and second controlled current sources are connected to the emitters of the first and second cascode transistors, respectively, and third and fourth controlled current sources are connected to the collectors thereof. A bias circuit controls the 4 controlled current sources in response to the emitter voltage of a pair of input transistors of an output stage the inputs of which are connected to the drains of the first and second cascode transistors.

Claims

1. An operational amplifier circuit comprising:

(a) an input stage including first and second input transistors coupled to a first tail current source and to first and second load devices, respectively;

(b) a folded cascode circuit including

i. first and second cascode transistors each having a first electrode, a second electrode, and a control electrode, the first electrode of the first cascode transistor being coupled by a first conductor to the first input transistor and the first load device, the first electrode of the second cascode transistor being coupled by a second conductor to the second input transistor and the second load device, the control electrodes being coupled to a first bias voltage,

ii. a first controlled current source coupled between the first electrode of the first cascode transistor and a first reference voltage, a second controlled current source coupled between the first electrode of the second cascode transistor and the first reference voltage, a third controlled current source coupled between the second electrode of the first cascode transistor and a second reference voltage, and a fourth controlled current source coupled between the second electrode of the second cascode transistor and the second reference voltage;

(c) a second stage having first and second inputs coupled to the second electrodes of the first and second cascode transistors, respectively, an output conductor for conducting an output signal, and a tail current conductor coupled to a second tail current source, the tail current conductor conducting a voltage representative of a common mode input voltage of the second stage, and first and second compensation capacitors coupled to the first and second inputs, respectively, of the output stage; and

(d) a bias circuit for biasing control terminals of the first, second, third, and fourth controlled current sources in response to the voltage conducted by the tail current conductor.

2. The operational amplifier circuit of claim 1 wherein the first and second cascode transistors are bipolar transistors, and wherein the first electrodes are emitters, the second electrodes are collectors, and the control electrodes are bases.

3. The operational amplifier circuit of claim 2 including a third compensation capacitor coupled to the first conductor and a fourth compensation capacitor coupled to the second conductor.

4. The operational amplifier circuit of claim 3 wherein the capacitance of the first compensation capacitor is approximately equal to the capacitance of the third compensation capacitor, and wherein the capacitance of the second compensation capacitor is approximately equal to the capacitance of the fourth compensation capacitor.

5. The operational amplifier circuit of claim 3 wherein the bias circuit is a class AB control circuit.

6. The operational amplifier of claim 1 wherein the bias circuit causes a quiescent current through the first and second cascode transistors to be substantially less than a tail current supplied by the tail current source.

7. The operational amplifier of claim 3 wherein the first and second input transistors are junction field effect transistors (JFETs) each having a source coupled to a first tail current source, drains of the first and second input transistors being coupled to the first and second conductors, respectively.

8. The operational amplifier of claim 3 wherein the first and second controlled current sources are NPN first and second transistors, and wherein the third and fourth controlled current sources are PNP third and fourth transistors.

9. The operational amplifier circuit of claim 8 wherein the bias circuit includes a first NPN bias transistor having a base coupled to receive a second bias voltage, an emitter coupled to the tail current conductor and to a collector and base of an NPN first current mirror input transistor and to bases of the NPN first and second transistors, the NPN first current mirror input transistor having an emitter coupled to the first reference voltage, the first NPN bias transistor having a collector coupled to a collector and base of a PNP second current mirror output transistor and to bases of the PNP third and fourth transistors, the PNP second current mirror output transistor having an emitter coupled to the second reference voltage.

10. The operational amplifier circuit of claim 3 wherein the second stage includes third and fourth input transistors, emitters of the third and fourth input transistors being coupled by the tail current conductor to the second tail current source, collectors of the third and fourth input transistors being coupled to a load circuit, the collector of the fourth input transistor being coupled to the output conductor.

11. The operational amplifier circuit of claim 10 wherein the load circuit includes a PNP current mirror input transistor having an emitter coupled to the second reference voltage and a base and collector connected to the collector of the third input transistor and a base of a PNP current mirror output transistor having an emitter coupled to the second reference voltage and to the output conductor.

12. A method of operating an amplifier circuit including (1) an input stage including first and second input transistors coupled to a first tail current source and to first and second load devices, respectively, and (2) a folded cascode circuit including first and second cascode transistors each having a first electrode, a second electrode, and a control electrode, the first electrode of the first cascode transistor being coupled by a first conductor to the first input transistor and the first load device, the first electrode of the second cascode transistor being coupled by a second conductor to the second input transistor and the second load device, the control electrodes being coupled to a first bias voltage, the method comprising:

(a) providing a first controlled current source coupled between the first electrode of the first cascode transistor and a first reference voltage, a second controlled current source coupled between the first electrode of the second cascode transistor and the first reference voltage, and also providing a third controlled current source coupled between the second electrode of the first cascode transistor and a second reference voltage, and a fourth controlled current source coupled between the second electrode of the second cascode transistor and the second reference voltage;

(b) providing a second stage having first and second inputs coupled to the second electrodes of the first and second cascode transistors, respectively, an output conductor for conducting an output signal, and a tail current conductor coupled to a second tail current source, the tail current conductor; and

(c) biasing control terminals of the first, second, third, and fourth controlled current sources by means of a bias circuit in response to a signal conducted by the tail current conductor.

13. The method of claim 12 including a first compensation capacitor between the first input of the second stage and one of the first and second reference voltages, and coupling a second compensation capacitor between the output conductor and the second input of the second stage.

14. The method of claim 12 including coupling a first compensation capacitor between the first input of the second stage and one of the first and second reference voltages, coupling a second compensation capacitor between the output conductor and the second input of the output stage, coupling a third compensation capacitor coupled between the first conductor and one of the first and second reference voltages, and coupling a fourth compensation capacitor between the output conductor and the second conductor.

15. The method of claim 14 including providing approximately equal capacitances for the first and third compensation capacitors and providing approximately equal capacitances for the second and fourth compensation capacitors.

16. The method of claim 12 including operating the bias circuit to cause quiescent currents through the first and second cascode transistors, respectively, to be substantially less than a tail current supplied by the first tail current source.

17. The method of claim 16 including operating the bias circuit to cause the quiescent currents to be sufficiently low to produce a predetermined low value of noise contribution by the first, second, third, and fourth controlled current sources.

18. The method of claim 16 including operating the bias circuit to determine a common mode input voltage of the second stage.

19. The method of claim 12 wherein step (c) includes biasing the control terminals of the first, second, third, and fourth controlled current sources by means of a class AB bias circuit.

20. An amplifier circuit including

(a) an input stage including first and second input transistors coupled to a first tail current source and to first and second load devices, respectively;

(b) a folded cascode circuit including first and second cascode transistors each having a first electrode, a second electrode, and a control electrode, the first electrode of the first cascode transistor being coupled by a first conductor to the first input transistor and the first load device, the first electrode of the second cascode transistor being coupled by a second conductor to the second input transistor and the second load device, the control electrodes being coupled to a first bias voltage;

(c) means for providing a first controlled current source coupled between the first electrode of the first cascode transistor and a first reference voltage, a second controlled current source coupled between the first electrode of the second cascode transistor and the first reference voltage, a third controlled current source coupled between the second electrode of the first cascode transistor and a second reference voltage, and a fourth controlled current source coupled between the second electrode of the second cascode transistor and the second reference voltage;

(d) output means having first and second inputs coupled to the second electrodes of the first and second cascode transistors, respectively, an output conductor for conducting an output signal, and a tail current conductor coupled to a second tail current source, the tail current conductor; and

(e) means for biasing control terminals of the first, second, third, and fourth controlled current sources in response to a signal conducted by the tail current conductor.