Circuit substrate and electronic apparatus, fabrication process thereof

• US 20070230151A1
• Filed: 08/22/2006
• Published: 10/04/2007
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Hayashi, Nobuyuki, Imanaka, Yoshihiko
• Granted Patent: US 7,468,490 B2
• Time in Patent Office: Days
• US Class Current: 361/795
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/0175 Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor
• CPC Class Codes: H05K 2201/0187 with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2201/09809 Coaxial layout reduction of cross-talk, noise or interference by printed shielding conductors for shielding around a single via or around a group of vias H05K1/0222
• CPC Class Codes: H05K 2201/09827 Tapered, e.g. tapered hole, via or groove bevelled, chamferred or tapered edge H05K2201/09154
• CPC Class Codes: H05K 2203/1366 Spraying coating apparatus for coating printed circuit boards using liquid non-metallic coating compositions H05K3/0091
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A circuit substrate comprises a lamination of plural resin insulation films and includes, on a surface and in an interior of the circuit substrate, plural interconnection layers. One of the plural resin insulation films is formed on a first conductor pattern constituting one of the plural interconnection layers in such a manner that a bottom principal surface of the resin insulation film makes a contact with a surface of the first conductor pattern, the resin insulation film including an opening defined by a sloped surface and exposing the first conductor pattern at the bottom principal surface. A ceramic high-K dielectric film is formed at a bottom of the opening in contact with the surface of the first conductor pattern, wherein there is formed a second conductor pattern constituting one of the plural interconnection layers on the resin insulation film so as to cover the sloped surface and in contact with a surface of the ceramic high-K dielectric film.

Claims

1. A circuit substrate comprising a lamination of plural resin insulation films and including, on a surface and in an interior of said circuit substrate, plural interconnection layers,

one of said plural resin insulation films being formed on a first conductor pattern constituting one of said plural interconnection layers in such a manner that a bottom principal surface of said resin insulation film makes a contact with a surface of said first conductor pattern,

said resin insulation film including an opening defined by a sloped surface and exposing said first conductor pattern at said bottom principal surface,

a ceramic high-K dielectric film being formed at a bottom of said opening in contact with said surface of said first conductor pattern,

wherein there is formed a second conductor pattern constituting one of said plural interconnection layers on said resin insulation film so as to cover said sloped surface and in contact with a surface of said ceramic high-K dielectric film.

2. The circuit substrate as claimed in claim 1, wherein said second conductor pattern is formed on a surface of said circuit substrate and a bump electrode of a semiconductor device is connected to said second conductor pattern.

3. An electronic apparatus, comprising:

a circuit substrate; and

a semiconductor device mounted upon said circuit substrate,

said circuit substrate comprising a lamination of plural resin insulation films and including, on a surface and in an interior of said circuit substrate, plural interconnection layers,

one of said plural resin insulation films being formed on a first conductor pattern constituting one of said plural interconnection layers in such a manner that a bottom principal surface of said resin insulation film makes a contact with a surface of said first conductor pattern,

said resin insulation film including an opening defined by a sloped surface and exposing said first conductor pattern at said bottom principal surface,

a ceramic high-K dielectric film being formed at a bottom of said opening in contact with said surface of said first conductor pattern,

wherein there is formed a second conductor pattern constituting one of said plural interconnection layers on said resin insulation film so as to cover said sloped surface and in contact with a surface of said ceramic high-K dielectric film.

4. A circuit substrate comprising a lamination of plural resin insulation films and including, on a surface and in an interior of said circuit substrate, plural interconnection layers, said circuit substrate comprising:

a first resin insulation film constituting one of said plural resin insulation films and formed over a first conductor pattern constituting one of said plural interconnection layers, in such a manner that a bottom principal surface of said first resin insulation film makes a contact with a surface of said first conductor pattern,

said first resin insulation film including a first opening defined by a sloped surface, said first opening exposing said first conductor pattern at a bottom of said first opening;

a lower electrode pattern formed over said first resin insulation film in contact with a surface of said first conductor pattern exposed at said bottom of said first opening, said lower electrode pattern having a shape conformal to a shape of said sloped surface of said first opening and having a depressed top surface corresponding to said first opening;

a second resin insulation film constituting one of said plural resin insulation films and formed over said first resin insulation film so as to cover said lower electrode pattern,

said second resin insulation film including a second opening formed in correspondence to said first opening and exposing said lower electrode pattern,

a ceramic high-K dielectric film formed in said second opening on said depressed top surface of said lower electrode pattern in conformity with a shape of said depressed top surface of said lower electrode pattern, said ceramic high-K dielectric film having a depressed top surface conformal to a shape of said depressed top surface of said lower electrode pattern,

wherein there is provided a second conductor pattern constituting one of said plural interconnection layers on said second resin insulation film such that said second conductor pattern makes a contact with said depressed top surface of said ceramic high-K dielectric film at said second opening.

5. The circuit substrate as claimed in claim 4, wherein said second conductor pattern is formed on said surface of said circuit substrate, and wherein a bump electrode of a semiconductor element is jointed to said second conductor pattern.

6. An electronic apparatus, comprising a circuit substrate and a semiconductor device mounted upon said circuit substrate, said circuit substrate comprising a lamination of plural resin insulation films and including, on a surface and in an interior of said circuit substrate, plural interconnection layers, said circuit substrate comprising:

a first resin insulation film constituting one of said plural resin insulation films and formed over a first conductor pattern constituting one of said plural interconnection layers, in such a manner that a bottom principal surface of said first resin insulation film makes a contact with a surface of said first conductor pattern,

said first resin insulation film including a first opening defined by a sloped surface, said first opening exposing said first conductor pattern at a bottom of said first opening;

a lower electrode pattern formed over said first resin insulation film in contact with a surface of said first conductor pattern exposed at said bottom of said first opening, said lower electrode pattern having a shape conformal to a shape of said sloped surface of said first opening and having a depressed top surface corresponding to said first opening;

a second resin insulation film constituting one of said plural resin insulation films and formed over said first resin insulation film so as to cover said lower electrode pattern,

said second resin insulation film including a second opening formed in correspondence to said first opening and exposing said lower electrode pattern,

a ceramic high-K dielectric film formed in said second opening on said depressed top surface of said lower electrode pattern in conformity with a shape of said depressed top surface of said lower electrode pattern, said ceramic high-K dielectric film having a depressed top surface conformal to a shape of said depressed top surface of said lower electrode pattern,

wherein there is provided a second conductor pattern constituting one of said plural interconnection layers on said second resin insulation film such that said second conductor pattern makes a contact with said depressed top surface of said ceramic high-K dielectric film at said second opening.

7. A method of producing a circuit substrate in the form of lamination of plural resin insulation films such that plural interconnection layers are formed on a surface and in an interior of said circuit substrate,

one of said plural resin insulation films being formed on a first conductor pattern constituting one of said plural interconnection layers in such a manner that a principal surface of said insulation film makes a contact with a surface of said first conductor pattern,

said method comprising the steps of:

forming an opening in said insulation film by a laser beam processing such that said first conductor pattern is exposed;

forming a ceramic high-K dielectric film at a bottom of said opening in contact with said first conductor pattern selectively by an aerosol deposition process; and

forming a second conductor pattern on said insulation film in contact with said high-K dielectric ceramic film in said opening.

8. A method of producing a circuit substrate in the form of lamination of plural resin insulation films such that plural interconnection layers are formed on a surface and in an interior of said circuit substrate, comprising the steps of:

forming a first insulation film constituting one of said plural resin insulation films on a first conductor pattern constituting one of said plural interconnection layers, such that a bottom principal surface of said first insulation film makes a contact with a surface of said first conductor pattern;

forming a first opening in said first insulation film by a laser beam processing such that said first opening exposes said conductor pattern;

forming a lower electrode pattern on said first insulation film so as to cover a sidewall surface of said first opening and make contact with said first conductor pattern at a bottom of said opening;

forming a second insulation film constituting one of said plural resin insulation films over said first insulation film so as to cover said lower electrode pattern;

forming a second opening in said second insulation film in correspondence to said first opening by a laser beam processing such that said second opening exposes said lower electrode pattern;

forming a ceramic high-K dialectic film on said exposed lower electrode pattern selectively by an aerosol deposition process; and

forming an upper electrode pattern on said second insulation film so as to cover said ceramic high-K dielectric film at said second opening.