Memory array with readout isolation

• US 20070230243A1
• Filed: 03/27/2007
• Published: 10/04/2007
• Est. Priority Date: 03/28/2006
• Status: Active Grant

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: Contour Semiconductor, Inc.
• Inventors: Nestler, Eric
• Granted Patent: US 7,593,256 B2
• Time in Patent Office: Days
• US Class Current: 365/175
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 8/10 Decoders

Abstract

Methods and apparatus for differentially measuring the bit state of a particular element in an array of passive nonlinear elements against the output of a reference generator. The reference generator may be, for example, a dummy row circuit, a dummy column circuit, or both a dummy row circuit and a dummy column circuit.

Claims

1. An information-storage circuit comprising:

a first set of generally parallel conductive lines;

a second set of generally parallel conductive lines that is generally perpendicular to and overlapping with the first set of lines;

a plurality of bit states, with each bit state of said plurality occurring in the general vicinity of a region of overlap between a line from the first set of lines and a line from the second set of lines, and the state of any bit state being determined by the presence or absence of a nonlinear element bridging a line from the first set of lines and a line from the second set of lines at a region of overlap;

a reference generator for providing a reference value adapted for measurement; and

state measurement circuitry for determining a selected bit state by comparing the state of a selected bit against the reference value.

2. The circuit of claim 1 wherein the state measurement circuitry measures the charge associated with a selected bit.

3. The circuit of claim 2 further comprising a plurality of capacitances, wherein each measured charge is stored on a capacitance.

4. The circuit of claim 1 further comprising a plurality of capacitances, wherein each capacitance is associated with one of said nonlinear elements.

5. The circuit of claim 4 wherein each capacitance occurs between one of said nonlinear elements and one line selected from said first set of lines or said second set of lines.

6. The circuit of claim 1 further comprising a plurality of capacitances, wherein each capacitance occurs between a first line from said first set of lines and a second line from said second set of lines.

7. The circuit of claim 1 wherein the state measurement circuitry comprises a comparator.

8. The circuit of claim 1 wherein the reference generator is a dummy row circuit.

9. The circuit of claim 1 wherein the reference generator is a dummy column circuit.

10. The circuit of claim 1 wherein the nonlinear element is selected from the group consisting of a diode, a series combination of a diode and a contact opening, and a series combination of a diode and a one-time programmable element.

21. The method of claim 11 wherein providing a plurality of bit states comprises providing a plurality of bit states, with each bit state of said plurality occurring in the general vicinity of a region of overlap between a line from the first set of lines and a line from the second set of lines, and the state of any bit state being determined by the presence or absence of a series combination of a diode and a contact opening bridging a line from the first set of lines and a line from the second set of lines at a region of overlap.

11. A method for determining bit state in an information-storage circuit, the method comprising:

providing a first set of generally parallel conductive lines;

providing a second set of generally parallel conductive lines that is generally perpendicular to and overlapping with the first set of lines;

providing a plurality of bit states, with each bit state of said plurality occurring in the general vicinity of a region of overlap between a line from the first set of lines and a line from the second set of lines, and the state of any bit state being determined by the presence or absence of a nonlinear element bridging a line from the first set of lines and a line from the second set of lines at a region of overlap;

providing a reference generator for providing a reference value adapted for measurement; and

providing state measurement circuitry for determining a selected bit state by comparing the state of a selected bit against the reference value.

12. The method of claim 11 wherein providing state measurement circuitry comprises providing state measurement circuitry that measures the charge associated with a selected bit.

13. The method of claim 12 further comprising providing a plurality of capacitances, wherein each measured charge is stored on a capacitance.

14. The method of claim 11 further comprising providing a plurality of capacitances, wherein each capacitance is associated with one of said nonlinear elements.

15. The method of claim 14 wherein each capacitance occurs between one of said nonlinear elements and one line selected from said first set of lines or said second set of lines.

16. The method of claim 11 further comprising providing a plurality of capacitances, wherein each capacitance occurs between a first line from said first set of lines and a second line from said second set of lines.

17. The method of claim 11 wherein providing state measurement circuitry comprises providing state measurement circuitry comprising a comparator.

18. The method of claim 17 wherein the comparator is operated synchronously with the information-storage circuit.

19. The method of claim 17 further comprising detecting a change using the comparator in at least one of charge, voltage and current to determine a digital output state.

20. The method of claim 11 wherein providing a plurality of bit states comprises providing a plurality of bit states, with each bit state of said plurality occurring in the general vicinity of a region of overlap between a line from the first set of lines and a line from the second set of lines, and the state of any bit state being determined by the presence or absence of a diode bridging a line from the first set of lines and a line from the second set of lines at a region of overlap.

22. The method of claim 11 wherein providing a plurality of bit states comprises providing a plurality of bit states, with each bit state of said plurality occurring in the general vicinity of a region of overlap between a line from the first set of lines and a line from the second set of lines, and the state of any bit state being determined by the presence or absence of a series combination of a diode and a one-time programmable element bridging a line from the first set of lines and a line from the second set of lines at a region of overlap.

23. The method of claim 11 wherein providing a reference generator comprises providing a dummy row circuit.

24. The method of claim 11 wherein providing a reference generator comprises providing a dummy column circuit.