Manufacturing method of wiring substrate and manufacturing method of semiconductor device

• US 20070231962A1
• Filed: 03/27/2007
• Published: 10/04/2007
• Est. Priority Date: 03/29/2006
• Status: Active Grant

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: Fujii, Tomoharu
• Granted Patent: US 7,841,076 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/142 Metallic substrates having insulating layers
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15321 being a ball array, e.g. BGA
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 13/106 Microstrip slot antennas patch antenna elements H01Q9/0407
• CPC Class Codes: H01Q 9/0407 Substantially flat resonant element parallel to ground plane, e.g. patch antenna dipole H01Q9/285; monopole H01Q9/40
• CPC Class Codes: H05K 1/056 the metal substrate being covered by an organic insulating layer
• CPC Class Codes: H05K 1/16 incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• CPC Class Codes: H05K 2203/0152 Temporary metallic carrier, e.g. for transferring material affixing a prefabricated conductor pattern formed by electroplating or electroforming on a metallic carrier H05K3/205
• CPC Class Codes: H05K 3/007 Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier H05K1/187, H05K3/20 and H05K3/4682 take precedence
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: Y10T 29/49002 Electrical device making
• CPC Class Codes: Y10T 29/49016 Antenna or wave energy "plumbing" making
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A multilayer wiring structural body 13 is formed on a surface 57A of a metal plate 57 used as a support plate in the case of forming the multilayer wiring structural body 13, and the metal plate 57 is patterned and a slot antenna 60 is formed.

Claims

1. A manufacturing method of a wiring substrate, including a multilayer wiring structural body having a wiring pattern and an insulating layer laminated, and an antenna disposed on one surface of said multilayer wiring structural body, an electronic component being mounted on the other surface opposite to the one surface of the multilayer wiring structural body, the manufacturing method comprising:

a multilayer wiring structural body formation step of forming the multilayer wiring structural body on a metal plate used as a support plate in the case of forming the multilayer wiring structural body; and

an antenna formation step of patterning the metal plate and forming the antenna.

2. A manufacturing method of a wiring substrate as claimed in claim 1, wherein the antenna formation step is performed before the multilayer wiring structural body formation step.

3. A manufacturing method of a wiring substrate, including a multilayer wiring structural body having a wiring pattern and an insulating layer laminated, and an antenna disposed on one surface of said multilayer wiring structural body, an electronic component being mounted on the other surface opposite to the one surface of the multilayer wiring structural body, the manufacturing method comprising:

a metal plate preparation step of preparing first and second metal plates used as support plates in the case of forming the multilayer wiring structural bodies;

a metal plate pasting step of pasting the first metal plate to the second metal plate so as to oppose a surface opposite to a surface of the first metal plate on which the multilayer wiring structural body is formed to a surface opposite to a surface of the second metal plate on which the multilayer wiring structural body is formed;

a multilayer wiring structural body formation step of simultaneously forming the multilayer wiring structural bodies on the first and second metal plates; and

an antenna formation step of patterning the first and second metal plates and forming the antennas in the first and second metal plates.

4. A manufacturing method of a wiring substrate as claimed in claim 3, wherein the antenna formation step is performed before the metal plate pasting step.

5. A manufacturing method of a wiring substrate as claimed in claim 3, further comprising:

a metal plate cut step of separating the first metal plate on which the multilayer wiring structural body is formed from the second metal plate on which the multilayer wiring structural body is formed by cutting the first and second metal plates after the multilayer wiring structural body formation step.

6. A manufacturing method of a semiconductor device, including a multilayer wiring structural body having a wiring pattern and an insulating layer laminated, an antenna disposed on one surface of said multilayer wiring structural body, and an electronic component which is disposed on the other surface opposite to the one surface of the multilayer wiring structural body and is electrically connected to the multilayer wiring structural body, the manufacturing method comprising:

a multilayer wiring structural body formation step of forming the multilayer wiring structural body on a metal plate used as a support plate in the case of forming the multilayer wiring structural body; and

an antenna formation step of patterning the metal plate and forming the antenna.

7. A manufacturing method of a semiconductor device as claimed in claim 6, wherein the antenna formation step is performed before the multilayer wiring structural body formation step.

8. A manufacturing method of a semiconductor device, including a multilayer wiring structural body having a wiring pattern and an insulating layer laminated, an antenna disposed on one surface of said multilayer wiring structural body, and an electronic component which is disposed on the other surface opposite to the one surface of the multilayer wiring structural body and is electrically connected to the multilayer wiring structural body, the manufacturing method comprising:

a metal plate preparation step of preparing first and second metal plates used as support plates in the case of forming the multilayer wiring structural bodies;

a metal plate pasting step of pasting the first metal plate to the second metal plate so as to oppose a surface opposite to a surface of the first metal plate on which the multilayer wiring structural body is formed to a surface opposite to a surface of the second metal plate on which the multilayer wiring structural body is formed;

a multilayer wiring structural body formation step of simultaneously forming the multilayer wiring structural bodies on the first and second metal plates; and

an antenna formation step of patterning the first and second metal plates and forming the antennas in the first and second metal plates.

9. A manufacturing method of a semiconductor device as claimed in claim 8, wherein the antenna formation step is performed before the metal plate pasting step.

10. A manufacturing method of a semiconductor device as claimed in claim 8, further comprising:

a metal plate cut step of separating the first metal plate on which the multilayer wiring structural body is formed from the second metal plate on which the multilayer wiring structural body is formed by cutting the first and second metal plates after the multilayer wiring structural body formation step.