In situ processing for ultra-thin gate oxide scaling

• US 20070232078A1
• Filed: 03/31/2006
• Published: 10/04/2007
• Est. Priority Date: 03/31/2006
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Kavalieros, Jack T., Doczy, Mark L., Dewey, Gilbert, Metz, Matthew V., Datta, Suman
• Application Number:
  US11/395,853
• Publication Number:
  US 20070232078A1
• Time in Patent Office: Days
• US Class Current: 438/778
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method including depositing a material for a gate electrode on a substrate over a dielectric material, the gate electrode material comprising a metal; depositing a capping material over the gate electrode material under processing conditions that will not promote any oxygen species associated with the gate electrode material to travel through the gate electrode material to the substrate; and patterning a gate electrode structure comprising the gate electrode material.

Claims

1. A method comprising:

depositing a material for a gate electrode on a substrate over a dielectric material, the gate electrode material comprising a metal;

depositing a capping material over the gate electrode material under processing conditions that will not promote any oxygen species associated with the gate electrode material to travel through the gate electrode material to the substrate; and

patterning a gate electrode structure comprising the gate electrode material.

2. The method of claim 1, wherein the capping material comprises silicon and depositing the capping material comprises physical vapor deposition.

3. The method of claim 1, wherein depositing the capping material comprises depositing under conditions where the wafer is at temperature of −

100°

C. to 225°

C.

4. The method of claim 1, wherein depositing the gate electrode material and depositing the capping material are done in situ.

5. The method of claim 1, wherein the dielectric material comprises a dielectric constant greater than a dielectric constant of silicon dioxide.

6. The method of claim 1, wherein the patterned gate electrode structure comprises the capping material.

12. The method of claim 1, wherein the patterned gate electrode structure comprises the capping material.

7. A method comprising:

depositing a material for a gate electrode on a substrate over a dielectric material, wherein the dielectric material has a dielectric constant greater than a dielectric constant of silicon dioxide;

depositing a capping material over the gate electrode material; and

patterning a gate electrode structure comprising the gate electrode material over a gate dielectric comprising the dielectric material,

wherein the capping material is deposited under processing conditions that do not increase an electrical thickness of the gate dielectric.

8. The method of claim 7, wherein the capping material comprises silicon and depositing the capping material comprises physical vapor deposition.

9. The method of claim 7, wherein depositing the capping material comprises depositing under conditions where the wafer is at temperature of −

100°

C. to 225°

C.

10. The method of claim 7, wherein depositing the gate electrode material and depositing the capping material are done in situ.

11. The method of claim 7, wherein the material for the gate electrode comprises a metal.

13. A method comprising:

depositing a material for a gate electrode on a substrate over a dielectric material, the gate electrode material comprising a metal;

depositing a capping material over the gate electrode material; and

patterning a gate electrode structure comprising the gate electrode material,

wherein depositing the material for the gate electrode and the capping material are done in situ.

14. The method of claim 13, wherein the dielectric material has a dielectric constant greater than a dielectric constant of silicon dioxide.

15. The method of claim 13, wherein the capping material comprises silicon and depositing the capping material comprises physical vapor deposition.

16. The method of claim 15, wherein depositing the capping material comprises depositing under conditions where the wafer is at temperature of −

100°

C. to 225°

C.