MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT

• US 20070232501A1
• Filed: 03/28/2007
• Published: 10/04/2007
• Est. Priority Date: 03/29/2006
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: TONOMURA, Osamu
• Granted Patent: US 7,592,272 B2
• Time in Patent Office: Days
• US Class Current: 505/473
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

An object of the present invention is to provide a method of depositing yttrium-stabilized hafnia use for a DRAM capacitor insulating film while controlling the composition at a high accuracy by an atomic layer deposition method. The atomic deposition method is performed by introducing a hafnium compound precursor, introducing a yttrium compound precursor and introducing an oxidant as one cycle. In the atomic deposition method, the addition amount of yttrium into hafnia is controlled accurately by controlling the time of introducing the hafnium compound precursor and the yttrium compound precursor and controlling the replacement ratio of OH groups on a sample surface by each of the precursors.

Claims

1. A method of manufacturing a semiconductor integrated circuit device provided with a memory cell having an information storing capacitor formed above a semiconductor substrate, wherein

the information storing capacitor has a lower electrode, an upper electrode, and an insulating film disposed between the lower electrode and the upper electrode,

the insulating film comprises a first element, a second element, and oxygen,

the insulating film is deposited by a method of alternately exposing a first precursor as a compound containing the first element, a second precursor as a compound containing the second element and an oxidant containing oxygen to a deposition surface, and

an adsorption ratio of the first precursor to the adsorption site on the deposition surface is 100% or less and the second precursor is adsorbed to the remaining adsorption site in the step of exposing the first precursor to the sample.

2. A method of manufacturing a semiconductor integrated circuit device provided with a memory cell having an information storing capacitor formed above a semiconductor substrate, wherein

the information storing capacitor has a lower electrode, an upper electrode, and an insulating film disposed between the lower electrode and the upper electrode,

the insulating film comprises a third element, a fourth element, and oxygen,

the insulating film is deposited by combining a first cycle of exposing a third precursor as a compound containing the third element to the deposition surface and then exposing an oxidant containing oxygen to the deposition surface, and a second cycle of exposing a fourth precursor as a compound containing the fourth element to the deposition surface and then exposing an oxidant containing oxygen to the deposition surface, and

substantially all the adsorption sites on the deposition surface are replaced with the third precursor by exposing the third precursor to the deposition surface, and substantially the all adsorption sites on the deposition surface are replaced with the fourth precursor by exposing the fourth precursor to the deposition surface.

3. A method of manufacturing a semiconductor integrated circuit device provided with a memory cell having an information storing capacitor formed above a semiconductor substrate, wherein

the information storing capacitor has a lower electrode, an upper electrode, and an insulating film disposed between the lower electrode and the upper electrode,

the insulating film comprises a fifth element, a sixth element, and oxygen,

the insulating film is deposited by repeating a third cycle of exposing a fifth precursor as a compound containing the fifth element and a sixth precursor as a compound containing the sixth element simultaneously on the deposition surface and then exposing an oxidant containing oxygen to the deposition surface, and

or less of adsorption sites on the deposition surface is replaced with the fifth precursor by exposing the fifth precursor and the sixth precursor to the deposition surface, and the remaining adsorption sites are replaced with the sixth precursor.

4. A method of manufacturing a semiconductor integrated circuit device provided with a memory cell having an information storing capacitor formed above a semiconductor substrate, wherein

the information storing capacitor has a lower electrode, an upper electrode and an insulating film disposed between the lower electrode and the upper electrode,

the insulating film comprises a seventh element, an eighth element, and oxygen,

the insulating film is deposited by combining a forth deposition cycle of exposing a seventh precursor containing the seventh element to a deposition surface and then exposing an oxidant containing oxygen to the deposition surface and a fifth deposition cycle of depositing the eighth element or an eighth oxide as the oxide of the eighth elements, and

substantially all the adsorption sites on the deposition surface are replaced with the seventh precursor by exposing the seventh precursor to the deposition surface.