Managing system availability

• US 20070233821A1
• Filed: 03/31/2006
• Published: 10/04/2007
• Est. Priority Date: 03/31/2006
• Status: Abandoned Application

• Current Assignee: EMC Corporation (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Sullivan, Douglas, Sardella, Steven, Morrissette, Keith
• Application Number:
  US11/394,699
• Publication Number:
  US 20070233821A1
• Time in Patent Office: Days
• US Class Current: 709/220
• CPC Class Codes: G06F 11/142 Reconfiguring to eliminate the error group management mechanisms in a peer-to-peer network H04L67/1044
• CPC Class Codes: G06F 11/1443 Transmit or communication errors
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: G06F 11/2089 Redundant storage control functionality
• CPC Class Codes: G06F 11/2289 by configuration test
• CPC Class Codes: H04L 41/0654 using network fault recovery ring fault isolation or reconfiguration in loop networks without recovery actions by a network management system H04L12/437

Abstract

System availability is managed. It is determined that a data communications link has been established and that the data communications link is less than fully functional. Communication is performed across the data communications link to a device to configure the device for the data communications link. The device is caused to re-establish the data communication link based on the results of the configuring.

Claims

1. A method for use in managing system availability, comprising:

determining that a data communications link has been established;

determining that the data communications link is less than fully functional;

communicating across the data communications link to a device to configure the device for the data communications link; and

causing the device to re-establish the data communication link based on the results of the configuring.

2. The method of claim 1, further comprising:

power cycling the device.

3. The method of claim 1, wherein the data communications link includes a PCI Express link.

4. The method of claim 1, further comprising:

communicating to the device through a Northbridge.

5. The method of claim 1, wherein the device includes a Fibre Channel controller.

6. The method of claim 1, further comprising:

communicating with the device via a Northbridge; and

communicating with a PCI Express switch via the Northbridge.

7. The method of claim 1, further comprising:

configuring the device for a high link width on the data communications link.

8. The method of claim 1, further comprising:

communicating with the device via a Northbridge;

issuing JTAG sequences to a PCI Express switch; and

communicating with the PCI Express switch via the Northbridge.

9. The method of claim 1, further comprising:

issuing JTAG sequences to the device.

10. The method of claim 1, further comprising:

programming an FPGA to issue JTAG sequences to the device.

11. The method of claim 1, further comprising:

communicating with the device via a Northbridge;

communicating with a PCI Express switch via the Northbridge; and

determining whether the PCI Express switch is configured to be driven by JTAG sequences.

12. The method of claim 1, further comprising:

saving register contents of the device before causing the device to re-establish the data communication link.

13. The method of claim 1, further comprising:

avoiding power cycling the device an excessive number of times.

14. The method of claim 1, further comprising:

communicating with the device via a Northbridge;

communicating with a PCI Express switch via the Northbridge; and

determining whether JTAG sequences have been successfully issued to the PCI Express switch.

15. The method of claim 1, further comprising:

determining whether an FPGA has already been programmed to issue JTAG sequences to the device.

16. The method of claim 1, further comprising:

determining that the data communications link does not includes as many lanes as desired.

17. A system for use in managing system availability, comprising:

a data storage system having a storage processor communicating with disk drives;

first logic determining that a data communications link has been established on the storage processor;

second logic determining that the data communications link is less than fully functional;

third logic communicating across the data communications link to a device to configure the device for the data communications link; and

fourth causing the device to re-establish the data communication link based on the results of the configuring.

18. The system of claim 17, wherein the data communications link includes a PCI

Express link.

19. The system of claim 17, wherein the device includes a Fibre Channel controller.

20. The system of claim 17, further comprising:

a Northbridge communicating with the device;

a PCI Express switch communicating with the Northbridge;

an FPGA issuing JTAG sequences to the device; and

a CPLD issuing JTAG sequences to the PCI Express switch.