Daisy chain cascade configuration recognition technique

• US 20070233903A1
• Filed: 11/29/2006
• Published: 10/04/2007
• Est. Priority Date: 03/28/2006
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Pyeon, Hong Beom
• Granted Patent: US 8,069,328 B2
• Time in Patent Office: Days
• US Class Current: 710/1
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

Methods and systems provide recognition of a device in a daisy chain cascade configuration. Input circuitry at a device receives an input signal that indicates device configuration following a power-up, reset or other operation of the device. A pulse generator generates a pulse in response to the operation, the pulse occurring while the input signal indicates device configuration. A state latch register stores the state of the input signal in response to the received pulse, thereby storing a state indicating configuration of the respective device. Following this operation, the input circuitry may receive signals unrelated to the device configuration, thereby obviating the need for additional pin assignment.

Claims

1. An apparatus for recognizing a daisy chain cascade configuration of devices, the apparatus comprising:

an input port at a memory device, the port receiving an input signal;

a signal generator that provides an indicator in response to an event, the indicator occurring during a time period in which the input signal indicates whether the memory device is configured in a daisy chain cascade configuration; and

a storage mechanism that stores a state of the input signal during the time period.

2. The apparatus of claim 1, wherein, following the time period, the input port receives a control signal associated with the memory device.

3. The apparatus of claim 2, wherein the control signal is a chip select signal.

4. The apparatus of claim 1, wherein the memory device is configured in a daisy chain cascade comprising a plurality of memory devices.

5. The apparatus of claim 4, wherein the plurality of memory devices include Flash memory devices in serial communication.

6. The apparatus of claim 1, wherein the signal generator receives an event signal corresponding to the event.

7. The apparatus of claim 1, wherein the event includes at least one of a powering up of the memory device and a reset of the memory device.

8. The apparatus of claim 1, wherein the memory device operates in a daisy chain cascade configuration in response to the state of the input signal indicating the daisy chain cascade configuration.

9. The apparatus of claim 1, wherein the register includes a state latch that latches the state of the input signal in response to the indicator.

10. A method of recognizing a daisy chain cascade configuration of devices, the method comprising:

receiving an input signal at an input port of a memory device;

generating a pulse in response to an event, the pulse occurring during a time period in which the input signal indicates whether the memory device is configured in a daisy chain cascade configuration; and

storing a state of the input signal during the time period.

11. The method of claim 10, further comprising receiving at the input port a control signal associated with the memory devices.

12. The method of claim 11, wherein the control signal is a chip select signal.

13. The method of claim 10, wherein the memory device is configured in a daisy chain cascade comprising a plurality of memory devices.

14. The method of claim 13, wherein the plurality of memory devices include Flash memory devices in serial communication.

15. The method of claim 10, further comprising receiving an event signal corresponding to the event.

16. The method of claim 10, wherein the event includes a powering up of the memory device.

17. The method of claim 10, wherein the event includes a reset of the memory device.

18. The method of claim 10, wherein the storing a state of the input signal includes latching the state of the input signal in response to the pulse.

19. A memory device comprising:

an input port; and

recognition circuitry that responds to an event to recognize the status of an input at the input port at a time of the event, the memory device being configured as a daisy chain cascade device dependent on the recognized status.

20. The device of claim 19, wherein, following the event, the input port receives a control signal associated with the memory device.

21. The device of claim 20, wherein the control signal is a chip select signal.

22. The device of claim 19, wherein the memory device is configured in a daisy chain cascade comprising a plurality of memory devices.

23. The device of claim 22, wherein the plurality of memory devices include Flash memory devices in serial communication.

24. The device of claim 19, wherein the event includes at least one of a powering up of the memory device and a reset of the memory device.

25. An apparatus for recognizing a daisy chain cascade configuration of devices, the apparatus comprising:

means for receiving an input signal at an input port of a memory device;

means for generating a pulse in response to an event, the pulse occurring during a time period in which the input signal indicates whether the memory device is configured in a daisy chain cascade configuration; and

means for storing a state of the input signal during the time period.

26. A system for recognizing a daisy chain cascade configuration of devices, the system comprising:

a plurality of memory devices;

a memory controller controlling the plurality of memory devices, the memory controller sending a signal to each of the plurality of memory devices; and

latching circuitry at each of the plurality of devices, the latching circuitry latching the signal during a time period in which the signal indicates configuration of the devices.

27. The system of claim 26, wherein the plurality of memory devices are configured in a daisy chain cascade arrangement.

28. The system of claim 27, wherein the signal indicates that the memory devices are configured in a daisy chain cascade arrangement.

29. The system of claim 26, wherein the plurality of memory devices include Flash memory.

30. The system of claim 26, wherein the time period follows at least one of a power up of the devices and a reset of the devices.

31. The system of claim 26, wherein, after the time period, the signal is a control signal.