FLASH MEMORY SYSTEM CONTROL SCHEME
First Claim
1. A method for controlling first and second Flash memory devices connected to a channel, comprising:
- a) executing a first operation in the first Flash memory device in response to a first command; and
,b) initiating a second operation in the second Flash memory device in response to a second command, while the first Flash memory device is executing the first operation.
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Accused Products
Abstract
A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the data to be programmed amongst the memory devices in the system, such that different pages of data are stored in different memory devices. A memory controller issues program commands for each memory device. As each memory device receives a program command, it either begins a programming operation or passes the command to the next memory device. Therefore, the memory devices in the Flash system sequentially program pages of data one after the other, thereby minimizing delay in programming each page of data into the Flash memory system. The memory controller can execute a wear leveling algorithm to maximize the endurance of each memory device, or to optimize programming performance and endurance for data of any size.
195 Citations
25 Claims
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1. A method for controlling first and second Flash memory devices connected to a channel, comprising:
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a) executing a first operation in the first Flash memory device in response to a first command; and
,b) initiating a second operation in the second Flash memory device in response to a second command, while the first Flash memory device is executing the first operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for high speed wear leveling programming in a Flash memory system having a plurality Flash memory devices, comprising:
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i. receiving a data file having k pages, k being an integer greater than 0; ii. selecting a programming profile corresponding to the size of k and configuration parameters of the Flash memory system; iii. programming at least one of the k pages of the data file in each of at least two of the plurality of Flash memory devices in accordance with the selected programming profile. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A data file structure for a memory system having at least two memory devices connected to the same channel, comprising:
portions of the data file stored in two of the at least two memory devices. - View Dependent Claims (19, 20)
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21. A method for high speed wear leveling programming in a Flash memory system having j Flash memory devices, each of the j Flash memory devices having i pages per block, where j and i are integer values greater than 0, the method comprising:
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a) receiving a data file having k pages, k being an integer greater than 0; b) providing commands for programming k pages within z of j memory devices if a ceiling function of z=k/i is less than or equal to j; c) providing commands for programming j*i pages within j memory devices if the ceiling function of z=k/i is greater than j; d) updating k by setting k=k−
(j*i); and
,e) repeating step b.
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22. A Flash memory system comprising:
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a controller having a channel for providing a first command and a second command; a first Flash memory device coupled to the channel for executing a first operation in response to the first command; and
,a second Flash memory device coupled to the channel for initiating a second operation in response to the second command while the first Flash memory device is executing the first operation. - View Dependent Claims (23, 24, 25)
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Specification