Systems and methods of selectively managing errors in memory modules

• US 20070234112A1
• Filed: 03/31/2006
• Published: 10/04/2007
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Thayer, Larry, Krejci, George, Cogdill, Mike, Walton, Andrew
• Granted Patent: US 8,612,797 B2
• Time in Patent Office: Days
• US Class Current: 714/8
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

System and methods of selectively managing errors in memory modules. In an exemplary implementation, a method may include monitoring for persistent errors in the memory modules. The methods may also include mapping at least a portion of the memory modules to a spare memory cache only to obviate persistent errors. The method may also include initiating memory erasure on at least a portion of the memory modules only if insufficient cache lines are available in the spare memory cache.

Claims

1. A method for selectively managing errors in memory modules, comprising:

monitoring for persistent errors in the memory modules;

mapping at least a portion of the memory modules to a spare memory cache only to obviate persistent errors; and

initiating memory erasure on at least a portion of the memory modules only if insufficient cache lines are available in the spare memory cache.

2. The method of claim 1, further comprising initiating page de-allocation for at least one of the memory modules only after using the spare memory cache and initiating memory erasure.

3. The method of claim 1, further comprising identifying at least one of the following in a memory management table:

portions of the memory modules memory mapped to the spare memory cache;

erased portions of the memory modules; and

de-allocated pages in the memory modules.

4. The method of claim 3, further comprising updating the memory management table to support memory migration.

5. The method of claim 1, further comprising identifying the portions of the memory modules for memory erasure based on hardware characteristics of the memory modules.

6. The method of claim 1, further comprising identifying the portions of the memory modules for memory erasure based on an error rate of the memory modules.

7. The method of claim 1, further comprising determining there are insufficient cache lines available in the spare memory cache if all of the cache lines are mapping memory modules with persistent errors.

8. The method of claim 1, further comprising determining there are insufficient cache lines available in the spare memory cache if additional cache lines are predicted to be needed before memory erasure frees the additional cache lines.

9. The method of claim 1, further comprising continuing mapping portions of the memory modules to the spare memory cache and continuing memory erasure after migrating at least one of the memory modules without having to rediscover the persistent errors.

10. A memory system comprising:

a memory controller for a plurality of memory modules;

a management processor operatively associated with the memory controller and a spare memory cache, the management processor executing;

program code for identifying errors in the memory modules;

program code selectively invoked to obviate persistent errors in the memory modules by routing at least some read/write requests to the spare memory cache; and

program code selectively invoked to erase a portion of the memory modules if the spare memory cache is exhausted.

11. The memory system of claim 10, further comprising program code selectively invoked to de-allocate one or more pages of the memory modules if at least some of the memory modules are erased.

12. The memory system of claim 10, further comprising a memory management table identifying memory management functions for the memory modules.

13. The memory system of claim 10, further the memory management table identifies erased portions of the memory modules.

14. The memory system of claim 13, wherein the memory management table identifies de-allocated pages in the memory modules.

15. The memory system of claim 10, further comprising program code for dynamically updating the memory management table.

16. The memory system of claim 10, further comprising program code for updating the memory management table for memory migration.

17. The memory system of claim 10, further the management processor writes to registers in the memory controller to reroute read/write requests for the memory modules to the spare memory cache using an out-of-band path.

18. The memory system of claim 10, further comprising program code for interfacing with a user during memory migration, the program code receiving memory migration information from the user and notifying the user if it is safe to proceed with the memory migration.

19. A system for selectively managing errors in memory modules, comprising:

means for identifying persistent errors in the memory modules;

means for rerouting 10 addressed to at least a portion of the memory modules instead to a spare memory cache only in response to persistent errors; and

means for erasing at least a portion of the memory modules only in response to all cache lines in the spare memory cache being used for the rerouted 10.

20. The system of claim 19, further comprising means for identifying memory management changes for continued memory operations after memory migration.