SEMICONDUCTOR MEMORY DEVICES AND METHODS OF TESTING FOR FAILED BITS OF SEMICONDUCTOR MEMORY DEVICES

• US 20070234143A1
• Filed: 03/20/2007
• Published: 10/04/2007
• Est. Priority Date: 01/25/2006
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Hyung-Min
• Application Number:
  US11/688,417
• Publication Number:
  US 20070234143A1
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/5606 Error catch memory
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

A semiconductor memory device includes a flash memory including a plurality of M-byte memory pages, and a buffer memory that includes a first M-byte buffer and a second M-byte buffer and that is configured to receive expected data used to test for failed bits in the flash memory. The semiconductor memory device further includes a fail-bit control unit configured to receive the expected data from the buffer memory, configured to receive the read data from the flash memory, and configured to calculate a failed bit number and a failed bit position in response to a mis-match between the expected data and the read data.

Claims

1. A semiconductor memory device comprising:

a flash memory comprising a plurality of M-byte memory pages;

a buffer memory configured to receive expected data used to test for failed bits in the flash memory, wherein the buffer memory comprises a first M-byte buffer and a second M-byte buffer; and

a fail-bit control unit configured to receive the expected data from the buffer memory, configured to receive the read data from the flash memory, and configured to calculate a failed bit number and a failed bit position in response to a mis-match between the expected data and the read data.

2. The semiconductor memory device of claim 1, further comprising an M-byte page buffer configured to receive read data from the flash memory, wherein the fail-bit control unit is configured to receive read data from the page buffer.

3. The semiconductor memory device of claim 1, wherein the expected data corresponds to a page of the flash memory, and wherein the buffer memory is further configured to receive the expected data in a single programming operation.

4. The semiconductor memory device of claim 1, wherein the buffer memory is configured to store expected data in the first buffer while the fail-bit control unit reads expected data from the second buffer.

5. The semiconductor memory device of claim 1, wherein the fail-bit control unit comprises:

a failed bit count unit configured to calculate the failed bit number in response to the expected data and the read data; and

a failed bit position unit configured to calculate the failed bit position in response to the expected data and the read data.

6. The semiconductor memory device of claim 5, wherein the failed bit count unit comprises:

a data comparator configured to compare the expected data with the read data; and

a failed bit counter configured to calculate the failed bit number from a comparison result of the data comparator.

7. The semiconductor memory device of claim 5, wherein the failed bit position unit comprises:

an expected data parity generator configured to generate an expected data parity value from the expected data;

a read data parity generator configured to generate a read data parity value from the read data; and

a failed bit position generator configured to calculate the failed bit position from the expected data parity value and the read data parity value.

8. The semiconductor memory device of claim 1, further comprising a failed bit register configured to store the failed bit number and the failed bit position.

9. A memory system, comprising:

a semiconductor memory device comprising;

a flash memory comprising a plurality of M-byte memory pages;

a buffer memory configured to receive expected data used to test for failed bits in the flash memory, wherein the buffer memory comprises a first M-byte buffer and a second M-byte buffer; and

a fail-bit control unit configured to receive the expected data from the buffer memory, configured to receive the read data from the flash memory, and configured to calculate a failed bit number and a failed bit position in response to the expected data and the read data;

a control unit configured to control a testing operation of the semiconductor memory device; and

a testing unit configured to store expected data in the buffer memory and configured to notify the control unit of a memory page of the flash memory to be tested.

10. The memory system of claim 9, wherein the testing unit is configured to store first expected data in the first buffer, and to store second expected data in the second buffer while the fail-bit control unit reads the first expected data from the first buffer.

11. A method of testing for failed bits in a semiconductor memory device including a flash memory and a buffer memory including first and second buffers, the method comprising:

loading expected data into the first buffer;

programming the expected data into the flash memory;

reading read data out from the flash memory;

reading the expected data from the first buffer; and

calculating a failed bit number and a failed bit position from the expected data and the read data.

12. The method of claim 11, wherein the expected data comprises first expected data, the method further comprising loading second expected data into the second buffer during reading of the second expected data from the first buffer.

13. The method of claim 12, further comprising loading a first pattern of expected data into the first buffer, and loading a second pattern of expected data into the second buffer, wherein the first pattern of expected data is different from the second pattern of expected data.

14. the method of claim 11, wherein reading read data out from the flash memory comprises reading read data from a page of the flash memory into a page buffer, and reading the read data from the page buffer.

15. The method of claim 11, wherein the expected data is loaded into the first buffer prior to testing, and the read data is read from the flash memory during testing.

16. The method of claim 11, wherein the first buffer comprises a plurality of memory segments, and wherein loading expected data into the first buffer comprises loading a plurality of different data patterns into the respective plurality of memory segments of the first buffer.

17. The method of claim 11, wherein calculating the failed bit number and the failed bit position comprises:

comparing the read data and the expected data to generate a comparison result; and

calculating the failed bit number based on the comparison result.

18. The method of claim 17, further comprising:

storing the failed bit number in a register; and

providing a testing unit with the failed bit number in response to a request signal from the testing unit.

19. The method of claim 11, wherein calculating the failed bit position comprises:

generating a read data parity value from the read data and an expected data parity value from the expected data, respectively; and

calculating the failed bit position from the read data parity value and the expected data parity value.

20. The method of claim 19, further comprising:

storing the failed bit position in a register; and

providing a testing unit with the failed bit number in response to a request signal from the testing unit.