Generating masking control circuits for test response compactors

• US 20070234169A1
• Filed: 02/20/2007
• Published: 10/04/2007
• Est. Priority Date: 02/17/2006
• Status: Abandoned Application

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Mrugalski, Grzegorz, Tyszer, Jerzy, Rajski, Janusz, Kassab, Mark
• Application Number:
  US11/708,717
• Publication Number:
  US 20070234169A1
• Time in Patent Office: Days
• US Class Current: 714/742
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test

Abstract

Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Claims

1. A method of testing a circuit-under-test, comprising:

during a first interval, providing test pattern data to inputs of a circuit-under-test; and

during a second interval, providing masking instructions for a masking circuit to the inputs of the circuit-under-test.

2. The method of claim 1, wherein the first interval precedes the second interval.

3. The method of claim 1, wherein the second interval precedes the first interval.

4. The method of claim 1, wherein the first interval comprises a third and a fourth interval and the second interval comprises a fifth and sixth interval, and wherein the third and fourth intervals are interspersed with the fifth and sixth intervals.

5. The method of claim 1, further comprising applying the masking instructions to a masking circuit as a test response to a test pattern generated from the test pattern data is being unloaded from the circuit-under-test.

6. The method of claim 1, further comprising applying the masking instructions to a masking circuit as a test response to a test pattern generated from other test pattern data is being unloaded from the circuit-under-test.

7. The method of claim 1, further comprising masking one or more test response bits according to the masking instructions.

8. A circuit configured to perform the method of claim 1.

9. A method of generating selection logic for a selection circuit used to control the masking of unknown states during test response compaction, the method comprising:

generating a candidate polynomial for possible inclusion in a set of accepted polynomials, the candidate polynomial and the accepted polynomials describing connections of two or more inputs of the selection logic to a respective output of the selection circuit;

selecting one or more test sets of polynomials, the test sets respectively comprising at least the candidate polynomial and one or more polynomials from the set of accepted polynomials;

computing rank values for the one or more test sets;

selecting the candidate polynomial for inclusion in the set of accepted polynomials based at least in part on the rank values; and

storing the set of accepted polynomials including the candidate polynomial on one or more computer-readable media.

10. The method of claim 9, further comprising:

generating a circuit description of the selection logic, the selection logic implementing polynomials from the set of accepted polynomials; and

storing the circuit description of the selection logic on one or more computer-readable media.

11. The method of claim 9, wherein the candidate polynomial is randomly generated.

12. The method of claim 9, further comprising:

determining whether the candidate polynomial shares more than a fixed number of terms with one or more of the polynomials in the set of accepted polynomials; and

generating a new candidate polynomial if the candidate polynomial does share more than the fixed number of terms with one or more of the polynomials in the set of accepted polynomials.

13. The method of claim 9, wherein the act of computing the rank values further comprises averaging the rank values for the two or more test sets of polynomials, and wherein the act of selecting the candidate polynomial is based at least in part on the average rank value.

14. The method of claim 9, further comprising repeating the acts of generating, selecting, and computing for a plurality of additional candidate polynomials.

15. The method of claim 14, wherein the act of selecting the candidate polynomial for inclusion in the accepted set of polynomials is further based on comparing the average rank value of the candidate polynomial with respective average rank values of the additional candidate polynomials.

16. The method of claim 9, wherein the act of computing the rank values for the two or more sets of polynomials comprises determining reduced-row echelon forms of the two or more test sets of polynomials.

17. One or more computer-readable media storing computer-executable instructions for causing a computer to perform the method of claim 9.

18. A method of generating masking instructions for a selection circuit operable to mask test response bits during testing of a circuit-under-test, the method comprising:

simulating a test pattern being applied to the circuit-under-test to produce a test response;

identifying one or more unknown states in the test response;

selecting one or more test response bits for masking based at least in part on the one or more identified unknown states; and

storing one or more indications of the selected test response bits on one or more computer-readable media.

19. The method of claim 18, further comprising encoding masking instructions for a selection circuit based at least in part on the selected one or more test response bits.

20. The method of claim 18, further comprising identifying one or more fault observation sites in the test response, the selection of the one or more test response bits for masking being further based at least in part on the one or more identified fault observation sites.

21. The method of claim 20, wherein the act of selecting one or more test response bits for masking comprises:

assigning weights to one or more scan cells of a selected scan chain of the circuit-under-test based at least in part on the one or more identified unknown states, the one or more identified fault observation sites, or both the one or more identified unknown states and the one or more identified fault observation sites;

aggregating the weights for one or more groups of scan cells within the selected scan chain;

computing one or more scores for the selected scan chain based at least in part on the aggregated weights; and

determining whether to mask test response bits from the selected scan chain based at least in part on the scores.

22. The method of claim 21, wherein the weights represent a type of value stored in the scan cells after the simulation of the test pattern being applied.

23. The method of claim 22, wherein one of the scores computed for the selected scan chain is proportional to an estimated number of errors that will be preserved if the selected scan chain is masked.

24. The method of claim 22, wherein one of the scores computed for the selected scan chain is proportional to an estimated number of errors that will be preserved if the selected scan chain is not masked.

25. A method of generating masking instructions for a selection circuit operable to mask test response bits during testing of a circuit, the method comprising:

assigning weights to one or more scan cells of a selected scan chain;

aggregating the weights for one or more groups of scan cells within the selected scan chain;

computing one or more scores for the selected scan chain based at least in part on the aggregated weights;

determining whether to mask test response bits from the selected scan chain based at least in part on the scores; and

storing an indication of the determination on one or more computer-readable media.

26. The method of claim 25, further comprising:

encoding masking instructions for the selection circuit based at least in part on the determination; and

storing the masking instructions on one or more computer-readable media.

27. The method of claim 25, wherein the weights represent a type of value stored in the scan cells after a test pattern is applied to a circuit-under-test.

28. The method of claim 25, wherein the act of assigning weights comprises assigning a first weight to a first respective scan cell in the selected scan chain that captures an unknown value.

29. The method of claim 28, wherein the act of assigning weights comprises assigning a second weight to a second respective scan cell in the selected scan chain that captures a value indicative of a targeted fault.

30. The method of claim 29, wherein the second weight is greater than the first weight.

31. The method of claim 29, wherein the act of assigning weights further comprises assigning a third weight to a third respective scan cell in the selected scan chain that capture a value that is neither unknown nor indicative of a targeted fault.

32. The method of claim 31, wherein the second weight is greater than both the first weight and the third weight, and wherein the third weight is greater than the first weight.

33. The method of claim 25, wherein one of the scores computed for the selected scan chain is proportional to an estimated number of errors that will be preserved if the selected scan chain is not masked.

34. The method of claim 25, wherein one of the scores computed for the selected scan chain is proportional to an estimated number of errors that will be preserved if the selected scan chain is masked.

35. The method of claim 25, further comprising repeating the acts of assigning, aggregating, and computing for one or more additional scan chains, thereby computing one or more scores for each of the one or more additional scan chain.

36. The method of claim 35, wherein the act of determining whether to mask test response bits from the selected scan chain further comprises comparing the one or more scores of the selected scan chain with the one or more scores for each respective additional scan chain.

37. One or more computer-readable media storing computer-executable instructions for causing a computer to perform the method of claim 25.