Error checking and correction (ECC) system and method

• US 20070234182A1
• Filed: 03/31/2006
• Published: 10/04/2007
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Wickeraad, John, Luk, King
• Granted Patent: US 8,245,109 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G11C 2029/1806 Address conversion or mapping, i.e. logical to physical address
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A method stores data and check bits for that data within a memory chip. The memory chip stores the data and check bits in a plurality of pages contained in the memory chip, each page including a plurality of storage locations with each storage location having an associated address. The method includes receiving data to be stored in the memory, calculating check bits for the received data, mapping the data to addresses associated with the storage locations in a given page in the memory chip, mapping the check bits to addresses associated with the storage locations contained in the same page as the data, and storing the data and check bits in the page. The method may be applied to a single memory chip or to multiple memory chips.

Claims

1. A method of storing data and check bits for that data within a memory chip, the memory chip storing the data and check bits in a plurality of pages contained in the memory chip, each page including a plurality of storage locations with each storage location having an associated address, the method comprising:

receiving data to be stored in the memory;

calculating check bits for the received data;

mapping the data to addresses associated with the storage locations in a given page in the memory chip;

mapping the check bits to addresses associated with the storage locations contained in the same page as the data; and

storing the data and check bits in the page.

2. The method of claim 1 wherein the check bits include error detection and correction bits that may be used for the detection of errors in the associated data stored in the same page as the check bits and also may be used for the correction of at least some detected errors in the associated data.

3. The method of claim 1 wherein the check bits comprise parity bits.

4. The method of claim 1 wherein the data stored in each page includes a plurality of data words, the data words collectively forming the data stored in the page and the method further comprising:

reading a data word stored in a page in the memory chip;

modifying the data word;

storing the modified data word in a buffer;

modifying the data to be stored in additional data words contained in the page; and

when all data words forming the data have been modified or in response to a triggering event,

obtaining the current values of all data words to be stored in the page;

from the current values of all the data words, generating new check bits for the data words; and

storing the new check bits and the current values for the data words in the page.

5. The method of claim 4 wherein the triggering event comprises receiving an address indicating data stored in another page in the memory chip is to be accessed.

6. The method of claim 1 further comprising reading data and check bits stored in pages in the memory chip, the operation of reading comprising:

reading the check bits from a given page;

after reading the check bits, sequentially reading data words that collectively form the data stored in the given page;

as each data word is read, using the check bits to determine whether there are any errors in the read data word.

7. The method of claim 1 wherein storing data and check bits for that data within the memory chip further comprises:

receiving data words to be written to a given page in the memory chip;

as each data word is received, generating corresponding check bits;

writing each data word to the corresponding page;

once all data words have for the page have been received, writing the check bits to the page.

8. The method of claim 1 wherein the data includes a plurality of bits and wherein storing the data and check bits in the page comprises storing respective bits in the form of a charge stored on a capacitor, with a first charge being stored when the bit has a first logic value and a second charge being stored when the bit has a second logic value.

9. A data path having a memory bus adapted to be coupled to a memory device and a processor bus adapted to be coupled to a processor, the data path being,

operable during a write mode of operation to receive on the processor bus respective data words to be stored in the memory device and to generate corresponding check bits for each received data word, the data path being further operable to store the data words and an error checking word including the check bits in a respective page in the memory device;

and

operable during a read mode of operation to receive on the memory bus the data words and the error checking word from a respective page in the memory device, and the data path being further operable to utilize the bits in the error checking word to detect errors in the received data words.

10. The data path of claim 9 wherein the data path is further operable during the write mode of operation to generate, as each data word is received, corresponding check bits in the error checking word, and the data path further operable to sequentially write each received data word to the corresponding page in the memory device, and operable after all data words of the page have been written to write the error checking word to the page.

11. The data path of claim 9 wherein the data path is further operable during the read mode of operation to first receive on the memory bus the error checking word from a given page being accessed and to thereafter sequentially receive data words on the memory bus that collectively form the data stored in the given page, and the data path being further operable to utilize the check bits in the error checking word to sequentially determine whether each received data word contains any errors as each data word is received.

12. The data path of claim 9 further comprising:

a data read path including,

a data output register coupled to the memory bus and operable to latch data bytes applied on the memory bus from a page being accessed, and operable to provide each latched data byte on an output;

a read check-bit register coupled to the output of the data output register to receive and store an ECC data byte corresponding to the first one of the data bytes latched by the data output register, and operable to sequentially output portions of the latched ECC data byte;

an ECC read word register coupled to the data output register to receive and store latched data bytes from the data output register, and operable to output data words, each data word corresponding to combination of two or more data bytes;

a multiplexer having a first input coupled to the ECC read word register, a second input, and a control input adapted to receive a read/write control signal, the multiplexer operable to provide data words from the ECC read word register on an output responsive to the read/write signal indicating a read operation;

an ECC logic circuit coupled to the output of the multiplexer and coupled to the read check-bit register, the ECC logic circuit operable during read operations to sequentially receive data words from the ECC read word register via the multiplexer and to sequentially receive portions of the ECC data byte from the read check-bit register, the ECC logic operable to determine whether each received data word contains any errors using the corresponding portion of the ECC data byte and to provide the data words on the processor bus along with an indication of whether any errors were detected.

13. The data path of claim 12 further comprising:

a data write path including,

a write merge logic circuit coupled to the processor bus and operable during write operations to latch data words applied on the processor bus and to provide the latched words on an output and operable during read-modify-write operations to latch a modified byte or bytes applied on the processor bus and to combine this modified byte or bytes with data words from the ECC logic circuit and provide these combined modified byte or bytes and data words on the output;

a write merge FIFO register coupled to the write merge logic circuit and having a first output coupled to the second input of the multiplexer and having a second output, the write merge FIFO operable during write operations to provide data words received from the write merge logic circuit on the second output and operable during read-modify-write operations to provide data words including the modified byte or bytes on the first output and to provide data bytes being written to the memory device on the second output;

a data input register coupled to the memory bus and having a first input coupled to the second output of the write merge FIFO and having a second input adapted to receive the ECC data byte corresponding to the data bytes in a given page, the data input register operable to apply data bytes received from the write merge FIFO on the memory bus and operable after all bytes in the given page have been applied on the memory bus to apply the ECC data byte on the memory bus;

a write check-bit register having a first input coupled to the ECC logic circuit to receive sequentially receive portions of a new ECC data byte generated by the ECC logic circuit during write operations, each portion corresponding to a value calculated for data words being written to the memory device during write operations, and the write check-bit register further including a second input coupled to the data output register to receive the ECC data byte for the page being accessed in the memory device during a read-modify-write operation, the write check-bit register being operable during read-modify-write operations to receive at least one new portion of the ECC data byte from the ECC logic circuit for the data word including the modified byte or bytes in the page being accessed, and to merge each new portion with the other unchanged portions of the ECC data byte and to output the ECC data byte including each new portion to the data input register;

the ECC logic circuit operable during write operations to receive data words being written to a page in the memory device from the multiplexer and operable to generate a portion of an ECC data byte for that page from each applied data word, and operable to apply each generated portion of the ECC data byte to the first input of the write check-bit register, and the ECC logic circuit operable during read modify write operations to supply to the first input of the write check-bit register the portion of ECC data byte corresponding to a data word including the modified byte or bytes.

14. The data path of claim 13 wherein the each data byte is 32-bits wide and each data word is 64-bits wide.

15. The data path of claim 9 further comprising a write coalescing buffer coupled to the processor bus, the write coalescing buffer operable to store modified bytes being written to a given page within the memory device until a triggering event occurs or until all bytes in that page have been modified, and operable during the write mode to thereafter supply all modified bytes to the data path for storage along with the corresponding check bits in a respective page in the memory device.

16. A memory system, comprising:

a memory device having address, data, and control busses collectively referred to as a memory bus;

a processor having address, data, and control bussed collectively referred to as a processor bus; and

a memory controller coupled to the memory bus of the memory device and coupled to the processor bus of the processor, the memory controller including a data path that is,

operable during a write mode of operation to receive on the processor bus respective data words to be stored in the memory device and to generate corresponding check bits for each received data word, the data path being further operable store the data words and an error checking word including the check bits in a respective page in the memory device; and

operable during a read mode of operation to receive on the memory bus the data words and the error checking word from a respective page in the memory device, and the data path being further operable to utilize the bits in the error checking word to detect errors in the received data words.

17. The memory system of claim 16 wherein the memory device comprises a single DRAM chip.

18. The memory system of claim 16 wherein the memory device comprises a plurality of DRAMs, with the data path being operable to store in each page of each of the memory devices data words and an error checking word corresponding to those data words.

19. The memory system of claim 16 wherein the memory controller further comprises address remap circuitry that is operable to remap logical addresses from the processor to physical addresses for the memory device such that the error checking word and the data words are stored in the same page in the memory device.

20. The memory system of claim 19 wherein the address remap circuitry executes an address remap algorithm that:

remaps logical addresses such that the least significant burst size bits (bits 5;

4) in the received logical address are mapped to the bank bits for the memory device to enable bank rotation within a 512-bit transfer;

remaps the logical address such that the row bits between the logical addresses and the corresponding physical addresses are the same, with the algorithm mapping physical address bits (3′

b111) to the column bits to thereby enable same page access for error check bit addresses and the corresponding data word addresses and to thereby map the most significant logical bits to the column bits; and

remaps the remaining address bits to increase page hit probability during sequential memory accesses to thereby improve performance of the processor.