Storage capacitor and method for producing such a storage capacitor

• US 20070235786A1
• Filed: 04/07/2006
• Published: 10/11/2007
• Est. Priority Date: 04/07/2006
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kapteyn, Christian, Kudelka, Stephan
• Application Number:
  US11/399,597
• Publication Number:
  US 20070235786A1
• Time in Patent Office: Days
• US Class Current: 257/301
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

A storage capacitor, particularly for use in a storage cell, exhibits two storage electrodes and a dielectric arranged between the two storage electrodes, an intermediate layer essentially consisting of carbon.

Claims

1. A storage capacitor for use in a storage cell, comprising:

two storage electrodes;

a dielectric arranged between the two storage electrodes; and

an intermediate layer which essentially consists of carbon.

2. The storage capacitor as claimed in claim 1, wherein the intermediate layer is a pure carbon layer.

3. A storage capacitor for use in a storage cell, comprising:

two storage electrodes;

a dielectric arranged between the two storage electrodes, one storage electrode exhibiting a first electrode layer;

an intermediate layer arranged on the first electrode layer and essentially consisting of carbon; and

a second electrode layer arranged on the intermediate layer.

4. The storage capacitor as claimed in claim 3, wherein the intermediate layer is a pure carbon layer.

5. The storage capacitor as claimed in claim 3, wherein the intermediate layer is 1 to 50 nm thick.

6. The storage capacitor as claimed in claim 3, wherein the first electrode layer consists of phosphorus-doped polysilicon.

7. The storage capacitor as claimed in claim 3, wherein the second electrode layer consists of arsenic-doped polysilicon.

8. A storage capacitor for use in a storage cell, comprising:

a trench being formed in a substrate;

a first storage electrode formed as an outer electrode in the substrate around the trench in a lower trench area;

a dielectric formed on the trench wall in the lower trench area;

an insulation layer formed adjoining the dielectric on the trench wall in an upper trench area; and

a second storage electrode formed as an inner electrode in the trench, the second storage electrode comprising a first electrode layer covering the dielectric, an intermediate layer arranged on the first electrode layer adjoining the insulation layer and essentially consisting of carbon and a second electrode layer arranged on the intermediate layer essentially filling the trench.

9. The storage capacitor as claimed in claim 8, wherein the intermediate layer is a pure carbon layer.

10. The storage capacitor as claimed in claim 8, wherein the intermediate layer is 1 to 50 nm thick.

11. A DRAM memory chip with DRAM storage cells which in each case exhibit a storage capacitor and a selection transistor, the storage capacitor comprising:

a first storage electrode formed as an outer electrode in a substrate around a trench in a lower trench area;

a dielectric formed on the trench wall in the lower trench area;

an insulation layer formed adjoining the dielectric on the trench wall in an upper trench area; and

a second storage electrode formed as inner electrode in the trench,

the second storage electrode comprising a first electrode layer covering the dielectric, an

intermediate layer arranged on the first electrode layer adjoining the insulation layer and a second electrode layer arranged on the intermediate layer essentially filling the trench,

the intermediate layer essentially consisting of carbon, and

the selection transistor exhibiting a first and a second source/drain electrode and a gate electrode and the one source/drain electrode of the selection transistor being electrically conductively connected to the inner electrode of the storage capacitor.

12. The DRAM memory chip as claimed in claim 11, wherein the intermediate layer is a pure carbon layer.

13. A storage capacitor for use in a storage cell, comprising:

two storage electrodes, one storage electrode exhibiting a metal layer;

a dielectric arranged between the two storage electrodes; and

an intermediate layer essentially consisting of carbon and being provided between the metal layer and a substrate.

14. The storage capacitor as claimed in claim 13, wherein the intermediate layer is a pure carbon layer.

15. The storage capacitor as claimed in claim 13, wherein the intermediate layer is 0.5 to 10 nm thick.

16. The storage capacitor as claimed in claim 13, wherein the substrate is a silicon substrate.

17. A storage capacitor for use in a storage cell, comprising:

two storage electrodes, one storage electrode exhibiting a metal layer;

a dielectric arranged between the two storage electrodes; and

an intermediate layer which essentially consists of carbon being provided between the metal layer and the dielectric.

18. The storage capacitor as claimed in claim 17, wherein the intermediate layer is a pure carbon layer.

19. The storage capacitor as claimed in claim 17, wherein the intermediate layer is 0.5 to 10 nm thick.

20. The storage capacitor as claimed in claim 17, wherein the dielectric is a high-k dielectric.

21. A method for producing a storage capacitor for use in a storage cell, comprising:

providing two storage electrodes;

arranging a dielectric arranged between the two storage electrodes; and

forming an intermediate layer which essentially consists of carbon.

22. The method as claimed in claim 21, wherein one storage electrode is formed with a first electrode layer, the intermediate layer arranged on the first electrode layer and essentially consisting of carbon and a second electrode layer arranged on the intermediate layer.

23. The method as claimed in claim 22, wherein the intermediate layer is formed as a pure carbon layer.

24. The method as claimed in claim 22, wherein the intermediate layer is applied in a thickness of 1 to 50 nm.

25. The method as claimed in claim 22, wherein the intermediate layer is pyrolytically applied.

26. The method as claimed in claim 22, wherein the first electrode layer is formed of phosphorus-doped polysilicon.

27. The method as claimed in claim 22, wherein the second electrode layer is formed of arsenic-doped polysilicon.

28. The method as claimed in claim 22, wherein

a trench is formed in a substrate,

one storage electrode formed as outer electrode in the substrate around the trench in a lower trench area,

the dielectric applied to the trench wall,

the trench being filled with the first electrode layer,

the first electrode layer removed from an upper trench area,

the dielectric exposed on the trench wall removed,

an insulation layer applied adjoining the dielectric on the trench wall in the upper trench area,

the intermediate layer being deposited,

the first electrode layer being covered completely and the insulation layer covered at least partially, and

the trench filled with the second electrode layer.

29. The method as claimed in claim 21, wherein

one storage electrode is formed with a metal layer, and

the intermediate layer which essentially consists of carbon is formed between the metal layer and a substrate.

30. The method as claimed in claim 29, wherein the intermediate layer is a pure carbon layer.

31. The method as claimed in claim 29, wherein the intermediate layer is 0.5 to 10 nm thick.

32. The method as claimed in claim 29, wherein the substrate is a silicon substrate.

33. The method as claimed in claim 21, wherein

one storage electrode is formed with a metal layer, and

the intermediate layer which essentially consists of carbon is formed between the metal layer and the dielectric.

34. The method as claimed in claim 33, wherein the intermediate layer is a pure carbon layer.

35. The method as claimed in claim 33, wherein the intermediate layer is 0.5 to 10 nm thick.

36. The method as claimed in claim 33, wherein the dielectric is a high-k dielectric.