Capacitor structure of semiconductor device and method of fabricating the same
First Claim
1. A method of fabricating a capacitor structure of a semiconductor device, comprising:
- forming an interlayer insulation layer on a semiconductor substrate;
forming a capacitor on the interlayer insulation layer, the capacitor including a bottom electrode, a dielectric layer pattern, and a top electrode;
forming a pad metal layer on the interlayer insulation layer to cover the capacitor; and
patterning the pad metal layer to form pads for bonding with external electronic devices and to form first and second upper interconnections connected to the top electrode and the bottom electrode, respectively.
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Accused Products
Abstract
A semiconductor device having superior capacitance may include interconnections formed on a semiconductor substrate, an interlayer insulation layer on the interconnections and having vias exposing a portion of the top surface of the interconnections, a capacitor which may be on the interlayer insulation layer and having a bottom electrode, a dielectric layer pattern, and a top electrode which may be sequentially stacked, and a pad structure may be connected to the interconnections through the vias. The pad structure may include pads for bonding with external electronic devices and a first upper interconnection connected to the top electrode of the capacitor.
26 Citations
21 Claims
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1. A method of fabricating a capacitor structure of a semiconductor device, comprising:
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forming an interlayer insulation layer on a semiconductor substrate; forming a capacitor on the interlayer insulation layer, the capacitor including a bottom electrode, a dielectric layer pattern, and a top electrode; forming a pad metal layer on the interlayer insulation layer to cover the capacitor; and patterning the pad metal layer to form pads for bonding with external electronic devices and to form first and second upper interconnections connected to the top electrode and the bottom electrode, respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of fabricating a capacitor structure of a semiconductor device, comprising:
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forming interconnections on a semiconductor substrate; forming an interlayer insulation layer having a mold opening and vias to expose a portion of a top surface of the interconnections; forming a capacitor on the mold opening and forming the interlayer insulation layer around the mold opening, the capacitor including a sequentially stacked bottom electrode, a dielectric layer pattern, and a top electrode; forming a pad metal layer covering the capacitor and filling the vias; patterning the pad metal layer to simultaneously form pads for bonding with external electronic devices and form an upper interconnection connected to a top electrode of the capacitor; and connecting the bottom electrode to the interconnection below the bottom electrode through the mold opening. - View Dependent Claims (14)
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15. A semiconductor device, comprising:
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interconnections on a semiconductor substrate; an interlayer insulation layer on the interconnections, the interlayer insulation layer having vias exposing a portion of a top surface of the interconnections; a capacitor on the interlayer insulation layer, the capacitor having a bottom electrode, a dielectric layer pattern, and a top electrode; and a pad structure connected to the interconnections through the vias, wherein the pad structure includes pads for bonding with external electronic devices and a first upper interconnection connected to the top electrode of the capacitor. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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Specification